Brendon Cahoon abf95a22c4 [Hexagon] Generate hardware loop for a vectorized loop ... The induction variable in the vectorized loop wasn't recognized properly, so a hardware loop wasn't generated. Differential Revision: http://reviews.llvm.org/D9722 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237388 91177308-0d34-0410-b5e6-96231b3b80d8		2015-05-14 20:36:19 +00:00
..
AArch64	Re-apply r237247 - [AArch64] Codegen VMAX/VMIN for safe math cases	2015-05-14 12:59:46 +00:00
ARM	[CodeGen] Use standard -not gnueabi- naming for f16 libcalls on Darwin.	2015-05-14 01:00:51 +00:00
BPF
CPP
Generic	[Statepoints] Support for "patchable" statepoints.	2015-05-12 23:52:24 +00:00
Hexagon	[Hexagon] Generate hardware loop for a vectorized loop	2015-05-14 20:36:19 +00:00
Inputs
Mips	[mips] Do not place users of $ra in the delay slot of call instructions.	2015-05-14 13:17:56 +00:00
MSP430
NVPTX
PowerPC	Fix test added in r236850 for OSX builders.	2015-05-08 14:04:54 +00:00
R600	R600/SI: add pass to mark CF live ranges as non-spillable	2015-05-12 17:13:02 +00:00
SPARC
SystemZ
Thumb
Thumb2
WinEH	Changed renaming of local symbols by inserting a dot vefore the numeric suffix.	2015-05-12 16:47:30 +00:00
X86	AVX-512: Added i1 type handling for calling conventions.	2015-05-14 09:04:45 +00:00
XCore