Dan Gohman 24bde5bce1 Don't narrow the load and store in a load+twiddle+store sequence unless ... there are clearly no stores between the load and the store. This fixes this miscompile reported as PR7833. This breaks the test/CodeGen/X86/narrow_op-2.ll optimization, which is safe, but awkward to prove safe. Move it to X86's README.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112861 91177308-0d34-0410-b5e6-96231b3b80d8		2010-09-02 21:18:42 +00:00
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Alpha	PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually	2010-08-01 21:13:28 +00:00
ARM	Fix an unnecessary XFAIL	2010-09-02 20:19:24 +00:00
Blackfin	Remove TargetInstrInfo::copyRegToReg entirely.	2010-07-11 17:01:17 +00:00
CBackend
CellSPU	Fix lowering of INSERT_VECTOR_ELT in SPU.	2010-08-29 12:41:50 +00:00
CPP
Generic	Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself	2010-07-27 18:02:18 +00:00
MBlaze
Mips	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
MSP430
PIC16
PowerPC	PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR.	2010-08-02 00:18:19 +00:00
SPARC
SystemZ	Correct bogus module triple specifications.	2010-08-30 10:48:29 +00:00
Thumb	Update test for 112609	2010-08-31 17:58:47 +00:00
Thumb2	Now that register allocation properly considers reserved regs, simplify the	2010-09-02 18:14:29 +00:00
X86	Don't narrow the load and store in a load+twiddle+store sequence unless	2010-09-02 21:18:42 +00:00
XCore