mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
5a70dd1d82
Similar to gep (r230786) and load (r230794) changes.
Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.
(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)
import fileinput
import sys
import re
rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)
def conv(match):
line = match.group(1)
line += match.group(4)
line += ", "
line += match.group(2)
return line
line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
sys.stdout.write(line[off:match.start()])
sys.stdout.write(conv(match))
off = match.end()
sys.stdout.write(line[off:])
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232184 91177308-0d34-0410-b5e6-96231b3b80d8
181 lines
6.7 KiB
LLVM
181 lines
6.7 KiB
LLVM
; Positive test for inline register constraints
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;
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; RUN: llc -march=mipsel < %s | FileCheck -check-prefix=CHECK_LITTLE_32 %s
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; RUN: llc -march=mips < %s | FileCheck -check-prefix=CHECK_BIG_32 %s
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%union.u_tag = type { i64 }
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%struct.anon = type { i32, i32 }
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@uval = common global %union.u_tag zeroinitializer, align 8
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; X with -3
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define i32 @constraint_X() nounwind {
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entry:
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;CHECK_LITTLE_32-LABEL: constraint_X:
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
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;CHECK_LITTLE_32: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,${2:X}", "=r,r,I"(i32 7, i32 -3) ;
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ret i32 0
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}
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; x with -3
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define i32 @constraint_x() nounwind {
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entry:
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;CHECK_LITTLE_32-LABEL: constraint_x:
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},0xfffd
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;CHECK_LITTLE_32: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,${2:x}", "=r,r,I"(i32 7, i32 -3) ;
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ret i32 0
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}
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; d with -3
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define i32 @constraint_d() nounwind {
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entry:
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;CHECK_LITTLE_32-LABEL: constraint_d:
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3
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;CHECK_LITTLE_32: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,${2:d}", "=r,r,I"(i32 7, i32 -3) ;
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ret i32 0
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}
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; m with -3
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define i32 @constraint_m() nounwind {
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entry:
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;CHECK_LITTLE_32-LABEL: constraint_m:
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-4
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;CHECK_LITTLE_32: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,${2:m}", "=r,r,I"(i32 7, i32 -3) ;
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ret i32 0
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}
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; z with -3
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define i32 @constraint_z() nounwind {
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entry:
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;CHECK_LITTLE_32-LABEL: constraint_z:
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},-3
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;CHECK_LITTLE_32: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 -3) ;
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; z with 0
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},$0
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;CHECK_LITTLE_32: #NO_APP
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tail call i32 asm sideeffect "addiu $0,$1,${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
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; z with non-zero and the "r"(register) and "J"(integer zero) constraints
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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;CHECK_LITTLE_32: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
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; z with zero and the "r"(register) and "J"(integer zero) constraints
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: mtc0 $0, ${{[0-9]+}}
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;CHECK_LITTLE_32: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
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; z with non-zero and just the "r"(register) constraint
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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;CHECK_LITTLE_32: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
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; z with zero and just the "r"(register) constraint
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; FIXME: Check for $0, instead of other registers.
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; We should be using $0 directly in this case, not real registers.
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; When the materialization of 0 gets fixed, this test will fail.
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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;CHECK_LITTLE_32: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
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ret i32 0
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}
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; a long long in 32 bit mode (use to assert)
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define i32 @constraint_longlong() nounwind {
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entry:
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;CHECK_LITTLE_32-LABEL: constraint_longlong:
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: addiu ${{[0-9]+}},${{[0-9]+}},3
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;CHECK_LITTLE_32: #NO_APP
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tail call i64 asm sideeffect "addiu $0,$1,$2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
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ret i32 0
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}
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; D, in little endian the source reg will be 4 bytes into the long long
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define i32 @constraint_D() nounwind {
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entry:
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;CHECK_LITTLE_32-LABEL: constraint_D:
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;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
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;CHECK_LITTLE_32: #NO_APP
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; D, in big endian the source reg will also be 4 bytes into the long long
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;CHECK_BIG_32-LABEL: constraint_D:
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;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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;CHECK_BIG_32: #APP
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;CHECK_BIG_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
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;CHECK_BIG_32: #NO_APP
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%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
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%trunc1 = trunc i64 %bosco to i32
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tail call i32 asm sideeffect "or $0,${1:D},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
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ret i32 0
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}
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; L, in little endian the source reg will be 0 bytes into the long long
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define i32 @constraint_L() nounwind {
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entry:
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;CHECK_LITTLE_32-LABEL: constraint_L:
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;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
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;CHECK_LITTLE_32: #NO_APP
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; L, in big endian the source reg will be 4 bytes into the long long
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;CHECK_BIG_32-LABEL: constraint_L:
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;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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;CHECK_BIG_32: #APP
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;CHECK_BIG_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
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;CHECK_BIG_32: #NO_APP
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%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
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%trunc1 = trunc i64 %bosco to i32
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tail call i32 asm sideeffect "or $0,${1:L},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
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ret i32 0
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}
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; M, in little endian the source reg will be 4 bytes into the long long
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define i32 @constraint_M() nounwind {
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entry:
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;CHECK_LITTLE_32-LABEL: constraint_M:
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;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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;CHECK_LITTLE_32: #APP
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;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
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;CHECK_LITTLE_32: #NO_APP
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; M, in big endian the source reg will be 0 bytes into the long long
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;CHECK_BIG_32-LABEL: constraint_M:
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;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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;CHECK_BIG_32: #APP
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;CHECK_BIG_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
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;CHECK_BIG_32: #NO_APP
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%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
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%trunc1 = trunc i64 %bosco to i32
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tail call i32 asm sideeffect "or $0,${1:M},$2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
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ret i32 0
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}
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