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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
3.2 KiB
LLVM
95 lines
3.2 KiB
LLVM
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic < %s | FileCheck %s -check-prefix=16
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@t = global i32 10, align 4
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@f = global i32 199, align 4
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@a = global i32 2, align 4
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@b = global i32 1000, align 4
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@c = global i32 2, align 4
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@z1 = common global i32 0, align 4
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@z2 = common global i32 0, align 4
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@z3 = common global i32 0, align 4
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@z4 = common global i32 0, align 4
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@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
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define void @calc_z() nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" {
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entry:
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%0 = load i32, i32* @a, align 4
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%cmp = icmp sge i32 %0, 1000
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br i1 %cmp, label %cond.true, label %cond.false
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cond.true: ; preds = %entry
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%1 = load i32, i32* @f, align 4
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br label %cond.end
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cond.false: ; preds = %entry
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%2 = load i32, i32* @t, align 4
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br label %cond.end
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cond.end: ; preds = %cond.false, %cond.true
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%cond = phi i32 [ %1, %cond.true ], [ %2, %cond.false ]
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store i32 %cond, i32* @z1, align 4
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%3 = load i32, i32* @b, align 4
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%cmp1 = icmp sge i32 %3, 1
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br i1 %cmp1, label %cond.true2, label %cond.false3
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cond.true2: ; preds = %cond.end
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%4 = load i32, i32* @t, align 4
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br label %cond.end4
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cond.false3: ; preds = %cond.end
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%5 = load i32, i32* @f, align 4
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br label %cond.end4
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cond.end4: ; preds = %cond.false3, %cond.true2
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%cond5 = phi i32 [ %4, %cond.true2 ], [ %5, %cond.false3 ]
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store i32 %cond5, i32* @z2, align 4
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%6 = load i32, i32* @c, align 4
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%cmp6 = icmp sge i32 %6, 2
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br i1 %cmp6, label %cond.true7, label %cond.false8
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cond.true7: ; preds = %cond.end4
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%7 = load i32, i32* @t, align 4
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br label %cond.end9
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cond.false8: ; preds = %cond.end4
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%8 = load i32, i32* @f, align 4
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br label %cond.end9
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cond.end9: ; preds = %cond.false8, %cond.true7
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%cond10 = phi i32 [ %7, %cond.true7 ], [ %8, %cond.false8 ]
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store i32 %cond10, i32* @z3, align 4
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%9 = load i32, i32* @a, align 4
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%cmp11 = icmp sge i32 %9, 2
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br i1 %cmp11, label %cond.true12, label %cond.false13
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cond.true12: ; preds = %cond.end9
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%10 = load i32, i32* @t, align 4
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br label %cond.end14
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cond.false13: ; preds = %cond.end9
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%11 = load i32, i32* @f, align 4
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br label %cond.end14
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cond.end14: ; preds = %cond.false13, %cond.true12
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%cond15 = phi i32 [ %10, %cond.true12 ], [ %11, %cond.false13 ]
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store i32 %cond15, i32* @z4, align 4
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ret void
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}
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attributes #0 = { nounwind "target-cpu"="mips16" "target-features"="+mips16,+o32" }
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attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" }
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; 16: slti ${{[0-9]+}}, 1000
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; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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; 16: slti ${{[0-9]+}}, 1 # 16 bit inst
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; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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; 16: slti ${{[0-9]+}}, 2 # 16 bit inst
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; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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; 16: slti ${{[0-9]+}}, 2 # 16 bit inst
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; 16: btnez $BB{{[0-9]+}}_{{[0-9]}}
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