llvm-6502/lib/CodeGen
Tom Stellard 4eccd9814f DAGCombine: Remove redundant NaN checks around ISD::FSQRT
This folds:

(select (setcc x, -0.0, *lt), NaN, (fsqrt x)) -> ( fsqrt x)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@235333 91177308-0d34-0410-b5e6-96231b3b80d8
2015-04-20 19:38:27 +00:00
..
AsmPrinter DebugInfo: Remove DIType 2015-04-20 18:52:06 +00:00
SelectionDAG DAGCombine: Remove redundant NaN checks around ISD::FSQRT 2015-04-20 19:38:27 +00:00
AggressiveAntiDepBreaker.cpp Correct the AggressiveAntiDepBreaker's handling of subregisters defining super registers 2015-01-28 14:44:14 +00:00
AggressiveAntiDepBreaker.h Use 'override/final' instead of 'virtual' for overridden methods 2015-04-11 02:11:45 +00:00
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp Replace std::copy with a back inserter with vector append where feasible 2015-02-28 10:11:12 +00:00
AntiDepBreaker.h
AtomicExpandPass.cpp Mutate TargetLowering::shouldExpandAtomicRMWInIR to specifically dictate how AtomicRMWInsts are expanded. 2015-03-04 15:47:57 +00:00
BasicTargetTransformInfo.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
BranchFolding.cpp BranchFolding: MergePotentialsElt has a total order, just call array_pod_sort. 2015-03-13 21:17:02 +00:00
BranchFolding.h
CalcSpillWeights.cpp Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool> 2014-11-19 07:49:26 +00:00
CallingConvLower.cpp musttail: Only set the inreg flag for fastcall and vectorcall 2015-01-12 23:28:23 +00:00
CMakeLists.txt Remove the Forward Control Flow Integrity pass and its dependencies. 2015-02-27 19:03:38 +00:00
CodeGen.cpp Reland r229944: EH: Prune unreachable resume instructions during Dwarf EH preparation 2015-03-09 22:45:16 +00:00
CodeGenPrepare.cpp [ARM] Align global variables passed to memory intrinsics 2015-04-13 10:47:39 +00:00
CriticalAntiDepBreaker.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
CriticalAntiDepBreaker.h Use 'override/final' instead of 'virtual' for overridden methods 2015-04-11 02:11:45 +00:00
DeadMachineInstructionElim.cpp Add the llvm.frameallocate and llvm.recoverframeallocation intrinsics 2015-01-13 00:48:10 +00:00
DFAPacketizer.cpp Remove the TargetMachine from DFAPacketizer since it was only 2014-10-14 01:03:16 +00:00
DwarfEHPrepare.cpp Stop calling DwarfEHPrepare from WinEHPrepare 2015-03-12 00:36:20 +00:00
EarlyIfConversion.cpp Add range iterators for post order and inverse post order. Use them 2015-04-15 17:41:42 +00:00
EdgeBundles.cpp
ErlangGC.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
ExecutionDepsFix.cpp remove function names from comments; NFC 2015-03-15 18:16:04 +00:00
ExpandISelPseudos.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
ExpandPostRAPseudos.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
GCMetadata.cpp [gcroot] Remove unused items from an enum 2015-04-02 05:02:16 +00:00
GCMetadataPrinter.cpp clang-format all the GC related files (NFC) 2015-01-16 23:16:12 +00:00
GCRootLowering.cpp Teach gcroot how to handle dynamically realigned frames 2015-04-02 05:00:40 +00:00
GCStrategy.cpp Revert GCStrategy ownership changes 2015-01-26 18:26:35 +00:00
GlobalMerge.cpp [GlobalMerge] Look at uses to create smaller global sets. 2015-04-18 01:21:58 +00:00
IfConversion.cpp [CodeGen][IfCvt] Don't re-ifcvt blocks with unanalyzable terminators. 2015-03-21 01:23:15 +00:00
InlineSpiller.cpp Use 'override/final' instead of 'virtual' for overridden methods 2015-04-11 02:11:45 +00:00
InterferenceCache.cpp Make static variables const if possible. Makes them go into a read-only section. 2015-03-08 16:07:39 +00:00
InterferenceCache.h Make static variables const if possible. Makes them go into a read-only section. 2015-03-08 16:07:39 +00:00
IntrinsicLowering.cpp
LatencyPriorityQueue.cpp Remove LatencyPriorityQueue::dump because it relies on an implicit copy ctor which is deprecated in C++11 (due to the presence of a user-declare dtor in the base class) 2015-03-03 21:16:56 +00:00
LexicalScopes.cpp DebugInfo: Gut DISubprogram and DILexicalBlock* 2015-04-14 03:40:37 +00:00
LiveDebugVariables.cpp DebugInfo: Fix UserValue::match() in LiveDebugVariables after r235050 2015-04-16 22:27:54 +00:00
LiveDebugVariables.h DebugInfo: Remove DIDescriptor from the DebugInfo API 2015-04-17 23:20:10 +00:00
LiveInterval.cpp Oops, didn't mean to commit my debug fprintfs 2015-04-08 02:10:01 +00:00
LiveIntervalAnalysis.cpp Do not track subregister liveness when it brings no benefits 2015-03-19 00:21:58 +00:00
LiveIntervalUnion.cpp LiveIntervalUnion: Allow specification of liverange when unifying/extracting. 2014-12-10 01:12:59 +00:00
LivePhysRegs.cpp More missing includes only visible to MSVC. 2015-03-23 18:23:08 +00:00
LiveRangeCalc.cpp Do not track subregister liveness when it brings no benefits 2015-03-19 00:21:58 +00:00
LiveRangeCalc.h Do not track subregister liveness when it brings no benefits 2015-03-19 00:21:58 +00:00
LiveRangeEdit.cpp MachineRegisterInfo can access TII off of the MachineFunction's 2015-01-27 01:15:16 +00:00
LiveRegMatrix.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
LiveStackAnalysis.cpp Recommit r231168: unique_ptrify LiveRange::segmentSet 2015-03-04 01:20:33 +00:00
LiveVariables.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp Use raw_pwrite_stream in the object writer/streamer. 2015-04-14 22:14:34 +00:00
LocalStackSlotAllocation.cpp [ARM] Fix handling of thumb1 out-of-range frame offsets 2015-03-20 17:20:07 +00:00
MachineBasicBlock.cpp Remove superfluous .str() and replace std::string concatenation with Twine. 2015-03-27 17:51:30 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp [MBP] Spell the conditions the same way through out this if statement. 2015-04-15 13:39:42 +00:00
MachineBranchProbabilityInfo.cpp
MachineCombiner.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
MachineCopyPropagation.cpp [MachineCopyPropagation] Fix a bug causing incorrect removal for the instruction sequences as follows 2015-03-13 05:15:23 +00:00
MachineCSE.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
MachineDominanceFrontier.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
MachineDominators.cpp MachineDominators: Move applySplitCriticalEdges into the cpp file. 2015-02-27 23:13:13 +00:00
MachineFunction.cpp Remove superfluous .str() and replace std::string concatenation with Twine. 2015-03-27 17:51:30 +00:00
MachineFunctionAnalysis.cpp Remove unused member variable. 2014-10-14 18:53:16 +00:00
MachineFunctionPass.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
MachineFunctionPrinterPass.cpp Rename argument strings of codegen passes to avoid collisions with command line 2014-12-13 04:52:04 +00:00
MachineInstr.cpp DebugInfo: Remove 'inlinedAt:' field from MDLocalVariable 2015-04-15 22:29:27 +00:00
MachineInstrBundle.cpp Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool> 2014-11-19 07:49:26 +00:00
MachineLICM.cpp [MachineLICM] Use newer model of register pressure sets. 2015-04-14 11:56:25 +00:00
MachineLoopInfo.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
MachineModuleInfo.cpp Revert r235154-r235156, they cause asserts when building win64 code (http://crbug.com/477988) 2015-04-17 09:10:43 +00:00
MachineModuleInfoImpls.cpp Clear the stub map in getSortedStubs. 2015-04-07 12:59:28 +00:00
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegionInfo.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
MachineRegisterInfo.cpp Have TargetRegisterInfo::getLargestLegalSuperClass take a 2015-03-10 23:46:01 +00:00
MachineScheduler.cpp Complete the MachineScheduler fix made way back in r210390. 2015-03-27 06:10:13 +00:00
MachineSink.cpp Use DomTree in MachineSink to sink over diamonds. 2014-12-04 10:36:42 +00:00
MachineSSAUpdater.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
MachineTraceMetrics.cpp Add range iterators for post order and inverse post order. Use them 2015-04-15 17:41:42 +00:00
MachineVerifier.cpp MachineVerifier: slightly simplify code that is only called with vregs 2015-03-25 21:18:22 +00:00
Makefile
module.modulemap
OcamlGC.cpp Revert GCStrategy ownership changes 2015-01-26 18:26:35 +00:00
OptimizePHIs.cpp Update SetVector to rely on the underlying set's insert to return a pair<iterator, bool> 2014-11-19 07:49:26 +00:00
Passes.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
PeepholeOptimizer.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
PHIElimination.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Use 'override/final' instead of 'virtual' for overridden methods 2015-04-11 02:11:45 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp [WinEH] Run cleanup handlers when an exception is thrown 2015-03-30 22:58:10 +00:00
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
RegAllocBase.h [RegAllocGreedy] Introduce a late pass to repair broken hints. 2015-01-08 01:16:39 +00:00
RegAllocBasic.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
RegAllocFast.cpp CodeGen: Stop using DIDescriptor::is*() and auto-casting 2015-04-06 23:27:40 +00:00
RegAllocGreedy.cpp RegAllocGreedy: Allow target to specify register class ordering. 2015-03-31 19:57:53 +00:00
RegAllocPBQP.cpp [PBQP] Use a local bit-matrix to speedup searching an edge in the graph. 2015-03-05 09:12:59 +00:00
RegisterClassInfo.cpp Have getRegPressureSetLimit take a MachineFunction so that a 2015-03-11 18:34:58 +00:00
RegisterCoalescer.cpp [RegisterCoalescer] Fix a potential misuse of direct operand index in the 2015-03-30 21:50:44 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Move private classes into anonymous namespaces 2015-03-23 12:30:58 +00:00
RegisterScavenging.cpp Grab the subtarget and subtarget dependent variables off of 2014-10-14 07:22:00 +00:00
ScheduleDAG.cpp Replace some uses of getSubtargetImpl with the cached version 2015-01-27 08:48:42 +00:00
ScheduleDAGInstrs.cpp DataLayout is mandatory, update the API to reflect it with references. 2015-03-10 02:37:25 +00:00
ScheduleDAGPrinter.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp Re-sort #include lines using my handy dandy ./utils/sort_includes.py 2015-02-13 09:09:03 +00:00
ShadowStackGCLowering.cpp [opaque pointer type] API migration for GEP constant factories 2015-04-02 18:55:32 +00:00
SjLjEHPrepare.cpp [opaque pointer type] More GEP API migrations 2015-04-04 21:07:10 +00:00
SlotIndexes.cpp [llvm] Replacing asserts with static_asserts where appropriate 2015-03-16 09:53:42 +00:00
Spiller.h [RegAlloc] Kill off the trivial spiller - nobody is using it any more. 2014-11-06 19:12:38 +00:00
SpillPlacement.cpp
SpillPlacement.h Use 'override/final' instead of 'virtual' for overridden methods 2015-04-11 02:11:45 +00:00
SplitKit.cpp LiveIntervalAnalysis: Factor out code to update liveness on vreg def removal 2015-01-21 19:02:30 +00:00
SplitKit.h
StackColoring.cpp CodeGen: Stop using DIDescriptor::is*() and auto-casting 2015-04-06 23:27:40 +00:00
StackMapLivenessAnalysis.cpp Internalize the StackMapLiveness pass. 2015-03-24 13:20:54 +00:00
StackMaps.cpp Remove dead calls and function arguments dealing with TRI in StackMaps. 2015-03-20 21:05:18 +00:00
StackProtector.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
StackSlotColoring.cpp Recommit r231175: Change LiveStackAnalysis::SS2IntervalMap from std::map to std::unordered_map 2015-03-04 01:15:53 +00:00
StatepointExampleGC.cpp Revert GCStrategy ownership changes 2015-01-26 18:26:35 +00:00
TailDuplication.cpp CodeGen: Canonicalize access to function attributes, NFC 2015-02-14 01:44:41 +00:00
TargetFrameLoweringImpl.cpp [X86] Convert esp-relative movs of function arguments to pushes, step 2 2015-02-01 16:56:04 +00:00
TargetInstrInfo.cpp Use the cached subtarget off of the machine function. 2015-03-19 23:06:21 +00:00
TargetLoweringBase.cpp Add support to promote f16 to f32 2015-04-17 18:36:25 +00:00
TargetLoweringObjectFileImpl.cpp Implement unique sections with an unique ID. 2015-04-04 18:02:01 +00:00
TargetOptionsImpl.cpp Remove CFIFuncName from TargetOptions as it is currently unused. 2015-04-19 03:21:04 +00:00
TargetRegisterInfo.cpp Introduce register dump helper 2014-11-19 19:46:11 +00:00
TargetSchedule.cpp Remove unnecessary TargetMachine.h includes. 2014-10-14 07:22:08 +00:00
TwoAddressInstructionPass.cpp Re-sort includes with sort-includes.py and insert raw_ostream.h where it's used. 2015-03-23 19:32:43 +00:00
UnreachableBlockElim.cpp Replace size method call of containers to empty method where appropriate 2015-01-15 11:41:30 +00:00
VirtRegMap.cpp Do not track subregister liveness when it brings no benefits 2015-03-19 00:21:58 +00:00
WinEHPrepare.cpp [WinEH] Fix memory leak with catch-all mapping. 2015-04-20 18:48:45 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str r4, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.