Quentin Colombet 5b00f4edcb Modify how the formulae are rated in Loop Strength Reduce. ... Namely, check if the target allows to fold more that one register in the addressing mode and if yes, adjust the cost accordingly. Prior to this commit, reg1 + scale * reg2 accesses were artificially preferred to reg1 + reg2 accesses. Indeed, the cost model wrongly assumed that reg1 + reg2 needs a temporary register for the computation, whereas it was correctly estimated for reg1 + scale * reg2. <rdar://problem/13973908> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183021 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-31 17:20:29 +00:00
..
AArch64	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
ARM	Revert r182937 and r182877.	2013-05-30 20:37:52 +00:00
CPP
Generic	Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen.	2013-05-21 14:37:16 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips	[mips] Big-endian code generation for atomic instructions.	2013-05-31 03:25:44 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX	[NVPTX] Re-enable support for virtual registers in the final output	2013-05-31 12:14:49 +00:00
PowerPC	Change how we iterate over relocations on ELF.	2013-05-30 03:05:14 +00:00
R600	R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg	2013-05-23 18:26:42 +00:00
SI
SPARC	[Sparc] Add support for leaf functions in sparc backend.	2013-05-29 04:46:31 +00:00
SystemZ	[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses	2013-05-31 13:25:22 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	Fix ARM FastISel tests, as a first step to enabling ARM FastISel	2013-05-14 16:26:38 +00:00
X86	Modify how the formulae are rated in Loop Strength Reduce.	2013-05-31 17:20:29 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00