llvm-6502/test/CodeGen
Reid Kleckner 504fa89c8e CodeGen support for x86_64 SEH catch handlers in LLVM
This adds handling for ExceptionHandling::MSVC, used by the
x86_64-pc-windows-msvc triple. It assumes that filter functions have
already been outlined in either the frontend or the backend. Filter
functions are used in place of the landingpad catch clause type info
operands. In catch clause order, the first filter to return true will
catch the exception.

The C specific handler table expects the landing pad to be split into
one block per handler, but LLVM IR uses a single landing pad for all
possible unwind actions. This patch papers over the mismatch by
synthesizing single instruction BBs for every catch clause to fill in
the EH selector that the landing pad block expects.

Missing functionality:
- Accessing data in the parent frame from outlined filters
- Cleanups (from __finally) are unsupported, as they will require
  outlining and parent frame access
- Filter clauses are unsupported, as there's no clear analogue in SEH

In other words, this is the minimal set of changes needed to write IR to
catch arbitrary exceptions and resume normal execution.

Reviewers: majnemer

Differential Revision: http://reviews.llvm.org/D6300

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225904 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-14 01:05:27 +00:00
..
AArch64 Fix PR22179. 2015-01-10 23:41:24 +00:00
ARM Debug info: Factor out the creation of DWARF expressions from AsmPrinter 2015-01-12 22:19:22 +00:00
CPP
Generic
Hexagon [Hexagon] Adding dealloc_return encoding and absolute address stores. 2015-01-06 16:15:15 +00:00
Inputs
Mips [mips][microMIPS] Fix issue with 16b instructions in jr instruction delay slot 2015-01-13 15:59:17 +00:00
MSP430
NVPTX
PowerPC Use the integrated assembler as default on PowerPC 2015-01-13 19:43:45 +00:00
R600 R600: Implement getRsqrtEstimate 2015-01-13 20:53:18 +00:00
SPARC
SystemZ Use the integrated assembler as default on SystemZ 2015-01-13 19:45:16 +00:00
Thumb
Thumb2 [ARM] Fix a bug in constant island pass that was triggering an assertion. 2015-01-08 20:44:50 +00:00
X86 CodeGen support for x86_64 SEH catch handlers in LLVM 2015-01-14 01:05:27 +00:00
XCore