Matt Arsenault 509a492442 Add target hook to prevent folding some bitcasted loads. ...

This is to avoid this transformation in some cases:
fold (conv (load x)) -> (load (conv*)x)

On architectures that don't natively support some vector
loads efficiently casting the load to a smaller vector of
larger types and loading is more efficient.

Patch by Micah Villmow.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8

2013-11-15 04:42:23 +00:00

..

CostTable.h

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Mangler.h

Move getSymbol to TargetLoweringObjectFile.

2013-10-29 17:28:26 +00:00

Target.td

[Stackmap] Add AnyReg calling convention support for patchpoint intrinsic.

2013-11-08 23:28:16 +00:00

TargetCallingConv.h

SelectionDAG: Pass along the original argument/element type in ISD::InputArg

2013-10-23 00:44:24 +00:00

TargetCallingConv.td

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TargetFrameLowering.h

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TargetInstrInfo.h

Fix the ExecutionDepsFix pass to handle AVX instructions.

2013-10-14 22:19:03 +00:00

TargetIntrinsicInfo.h

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TargetItinerary.td

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TargetJITInfo.h

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TargetLibraryInfo.h

Convert calls to __sinpi and __cospi into __sincospi_stret

2013-11-03 06:48:38 +00:00

TargetLowering.h

Add target hook to prevent folding some bitcasted loads.

2013-11-15 04:42:23 +00:00

TargetLoweringObjectFile.h

Move getSymbol to TargetLoweringObjectFile.

2013-10-29 17:28:26 +00:00

TargetMachine.h

Move the old pass manager infrastructure into a legacy namespace and

2013-11-09 12:26:54 +00:00

TargetOpcodes.h

Lower stackmap intrinsics directly to their target opcode in the DAG builder.

2013-10-31 17:18:24 +00:00

TargetOptions.h

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TargetRegisterInfo.h

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TargetSchedule.td

Even more spelling fixes for "instruction".

2013-09-28 13:42:22 +00:00

TargetSelectionDAG.td

Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift instructions:

2013-09-04 09:28:24 +00:00

TargetSelectionDAGInfo.h

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TargetSubtargetInfo.h

Added temp flag -misched-bench for staging in default changes.

2013-09-26 05:53:35 +00:00