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llvm-6502/test/CodeGen/PowerPC/vec_extload.ll
Benjamin Kramer 4dc478308f When lowering an inreg sext first shift left, then right arithmetically. 
Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172322 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-12 19:06:44 +00:00

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