llvm-6502

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Juergen Ributzka 5273295751 [FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.

This fixes a bug I introduced in a previous commit (r216033). Sign-/Zero-
extension from i1 cannot be folded into the ADDS/SUBS instructions. Instead both
operands have to be sign-/zero-extended with separate instructions.

Related to <rdar://problem/17913111>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216073 91177308-0d34-0410-b5e6-96231b3b80d8

2014-08-20 16:34:15 +00:00

AArch64

[FastISel][AArch64] Don't fold the sign-/zero-extend from i1 into the compare.

2014-08-20 16:34:15 +00:00

ARM

ARM: Fix codegen for rbit intrinsic

2014-08-20 10:40:20 +00:00

CPP

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