mirror of
https://github.com/c64scene-ar/llvm-6502.git
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49683f3c96
The new target machines are: nvptx (old ptx32) => 32-bit PTX nvptx64 (old ptx64) => 64-bit PTX The sources are based on the internal NVIDIA NVPTX back-end, and contain more functionality than the current PTX back-end currently provides. NV_CONTRIB git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156196 91177308-0d34-0410-b5e6-96231b3b80d8
174 lines
4.5 KiB
LLVM
174 lines
4.5 KiB
LLVM
; RUN: llc < %s -march=nvptx -mcpu=sm_10 | FileCheck %s --check-prefix=PTX32
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; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s --check-prefix=PTX32
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_10 | FileCheck %s --check-prefix=PTX64
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; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck %s --check-prefix=PTX64
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;; i8
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define i8 @ld_global_i8(i8 addrspace(1)* %ptr) {
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; PTX32: ld.global.u8 %rc{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.global.u8 %rc{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i8 addrspace(1)* %ptr
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ret i8 %a
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}
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define i8 @ld_shared_i8(i8 addrspace(3)* %ptr) {
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; PTX32: ld.shared.u8 %rc{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.shared.u8 %rc{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i8 addrspace(3)* %ptr
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ret i8 %a
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}
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define i8 @ld_local_i8(i8 addrspace(5)* %ptr) {
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; PTX32: ld.local.u8 %rc{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.local.u8 %rc{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i8 addrspace(5)* %ptr
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ret i8 %a
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}
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;; i16
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define i16 @ld_global_i16(i16 addrspace(1)* %ptr) {
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; PTX32: ld.global.u16 %rs{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.global.u16 %rs{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i16 addrspace(1)* %ptr
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ret i16 %a
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}
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define i16 @ld_shared_i16(i16 addrspace(3)* %ptr) {
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; PTX32: ld.shared.u16 %rs{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.shared.u16 %rs{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i16 addrspace(3)* %ptr
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ret i16 %a
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}
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define i16 @ld_local_i16(i16 addrspace(5)* %ptr) {
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; PTX32: ld.local.u16 %rs{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.local.u16 %rs{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i16 addrspace(5)* %ptr
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ret i16 %a
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}
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;; i32
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define i32 @ld_global_i32(i32 addrspace(1)* %ptr) {
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; PTX32: ld.global.u32 %r{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.global.u32 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i32 addrspace(1)* %ptr
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ret i32 %a
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}
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define i32 @ld_shared_i32(i32 addrspace(3)* %ptr) {
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; PTX32: ld.shared.u32 %r{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.shared.u32 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i32 addrspace(3)* %ptr
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ret i32 %a
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}
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define i32 @ld_local_i32(i32 addrspace(5)* %ptr) {
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; PTX32: ld.local.u32 %r{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.local.u32 %r{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i32 addrspace(5)* %ptr
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ret i32 %a
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}
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;; i64
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define i64 @ld_global_i64(i64 addrspace(1)* %ptr) {
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; PTX32: ld.global.u64 %rl{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.global.u64 %rl{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i64 addrspace(1)* %ptr
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ret i64 %a
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}
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define i64 @ld_shared_i64(i64 addrspace(3)* %ptr) {
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; PTX32: ld.shared.u64 %rl{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.shared.u64 %rl{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i64 addrspace(3)* %ptr
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ret i64 %a
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}
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define i64 @ld_local_i64(i64 addrspace(5)* %ptr) {
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; PTX32: ld.local.u64 %rl{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.local.u64 %rl{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load i64 addrspace(5)* %ptr
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ret i64 %a
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}
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;; f32
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define float @ld_global_f32(float addrspace(1)* %ptr) {
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; PTX32: ld.global.f32 %f{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.global.f32 %f{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load float addrspace(1)* %ptr
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ret float %a
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}
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define float @ld_shared_f32(float addrspace(3)* %ptr) {
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; PTX32: ld.shared.f32 %f{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.shared.f32 %f{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load float addrspace(3)* %ptr
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ret float %a
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}
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define float @ld_local_f32(float addrspace(5)* %ptr) {
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; PTX32: ld.local.f32 %f{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.local.f32 %f{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load float addrspace(5)* %ptr
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ret float %a
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}
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;; f64
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define double @ld_global_f64(double addrspace(1)* %ptr) {
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; PTX32: ld.global.f64 %fl{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.global.f64 %fl{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load double addrspace(1)* %ptr
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ret double %a
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}
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define double @ld_shared_f64(double addrspace(3)* %ptr) {
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; PTX32: ld.shared.f64 %fl{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.shared.f64 %fl{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load double addrspace(3)* %ptr
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ret double %a
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}
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define double @ld_local_f64(double addrspace(5)* %ptr) {
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; PTX32: ld.local.f64 %fl{{[0-9]+}}, [%r{{[0-9]+}}]
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; PTX32: ret
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; PTX64: ld.local.f64 %fl{{[0-9]+}}, [%rl{{[0-9]+}}]
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; PTX64: ret
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%a = load double addrspace(5)* %ptr
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ret double %a
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}
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