mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
166 lines
4.8 KiB
LLVM
166 lines
4.8 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s
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; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s
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;FUNC-LABEL: {{^}}test1:
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: v_add_i32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}}
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;SI-CHECK-NOT: [[REG]]
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;SI-CHECK: buffer_store_dword [[REG]],
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define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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%b_ptr = getelementptr i32 addrspace(1)* %in, i32 1
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%a = load i32 addrspace(1)* %in
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%b = load i32 addrspace(1)* %b_ptr
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%result = add i32 %a, %b
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store i32 %result, i32 addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: {{^}}test2:
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32> addrspace(1)* %in
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%b = load <2 x i32> addrspace(1)* %b_ptr
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%result = add <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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;FUNC-LABEL: {{^}}test4:
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
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define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32> addrspace(1)* %in
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%b = load <4 x i32> addrspace(1)* %b_ptr
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%result = add <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test8:
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) {
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entry:
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%0 = add <8 x i32> %a, %b
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store <8 x i32> %0, <8 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test16:
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; EG-CHECK: ADD_INT
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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; SI-CHECK: s_add_i32
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define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) {
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entry:
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%0 = add <16 x i32> %a, %b
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store <16 x i32> %0, <16 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}add64:
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; SI-CHECK: s_add_u32
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; SI-CHECK: s_addc_u32
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define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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entry:
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%0 = add i64 %a, %b
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store i64 %0, i64 addrspace(1)* %out
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ret void
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}
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; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
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; use VCC. The test is designed so that %a will be stored in an SGPR and
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; %0 will be stored in a VGPR, so the comiler will be forced to copy %a
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; to a VGPR before doing the add.
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; FUNC-LABEL: {{^}}add64_sgpr_vgpr:
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; SI-CHECK-NOT: v_addc_u32_e32 s
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define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) {
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entry:
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%0 = load i64 addrspace(1)* %in
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%1 = add i64 %a, %0
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store i64 %1, i64 addrspace(1)* %out
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ret void
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}
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; Test i64 add inside a branch.
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; FUNC-LABEL: {{^}}add64_in_branch:
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; SI-CHECK: s_add_u32
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; SI-CHECK: s_addc_u32
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define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) {
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entry:
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%0 = icmp eq i64 %a, 0
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br i1 %0, label %if, label %else
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if:
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%1 = load i64 addrspace(1)* %in
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br label %endif
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else:
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%2 = add i64 %a, %b
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br label %endif
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endif:
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%3 = phi i64 [%1, %if], [%2, %else]
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store i64 %3, i64 addrspace(1)* %out
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ret void
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}
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