mirror of
https://github.com/c64scene-ar/llvm-6502.git
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8eaed0f63d
This matches the format produced by the AMD proprietary driver.
//==================================================================//
// Shell script for converting .ll test cases: (Pass the .ll files
you want to convert to this script as arguments).
//==================================================================//
; This was necessary on my system so that A-Z in sed would match only
; upper case. I'm not sure why.
export LC_ALL='C'
TEST_FILES="$*"
MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r`
for f in $TEST_FILES; do
# Check that there are SI tests:
grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f
if [ $? -eq 0 ]; then
for match in $MATCHES; do
sed -i -e "s/\([ :]$match\)/\L\1/" $f
done
# Try to get check lines with partial instruction names
sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f
fi
done
sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll
sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll
sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll
sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll
sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll
//==================================================================//
// Shell script for converting .td files (run this last)
//==================================================================//
export LC_ALL='C'
sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td
sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221350 91177308-0d34-0410-b5e6-96231b3b80d8
70 lines
2.7 KiB
LLVM
70 lines
2.7 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs< %s
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
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declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
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; FUNC-LABEL: {{^}}uaddo_i64_zext:
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; SI: add
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; SI: addc
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; SI: addc
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define void @uaddo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind {
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%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind
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%val = extractvalue { i64, i1 } %uadd, 0
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%carry = extractvalue { i64, i1 } %uadd, 1
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%ext = zext i1 %carry to i64
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%add2 = add i64 %val, %ext
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store i64 %add2, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_uaddo_i32:
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; SI: s_add_i32
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define void @s_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) nounwind {
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) nounwind
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_i32:
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; SI: v_add_i32
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define void @v_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) nounwind {
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%a = load i32 addrspace(1)* %aptr, align 4
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%b = load i32 addrspace(1)* %bptr, align 4
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b) nounwind
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}s_uaddo_i64:
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; SI: s_add_u32
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; SI: s_addc_u32
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define void @s_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) nounwind {
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%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind
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%val = extractvalue { i64, i1 } %uadd, 0
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%carry = extractvalue { i64, i1 } %uadd, 1
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store i64 %val, i64 addrspace(1)* %out, align 8
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_i64:
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; SI: v_add_i32
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; SI: v_addc_u32
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define void @v_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind {
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%a = load i64 addrspace(1)* %aptr, align 4
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%b = load i64 addrspace(1)* %bptr, align 4
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%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b) nounwind
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%val = extractvalue { i64, i1 } %uadd, 0
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%carry = extractvalue { i64, i1 } %uadd, 1
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store i64 %val, i64 addrspace(1)* %out, align 8
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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