Matt Arsenault ab5382f5eb R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp ...

Remove handling of select_cc, since it makes no sense to be there. This
now does nothing, but I'll be adding some handling of other target nodes
soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204743 91177308-0d34-0410-b5e6-96231b3b80d8

2014-03-25 18:18:27 +00:00

..

InstPrinter

Make methods static

2014-03-17 22:23:09 +00:00

MCTargetDesc

Fix missing C++ mode comment

2014-03-06 17:33:58 +00:00

TargetInfo

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AMDGPU.h

…

AMDGPU.td

…

AMDGPUAsmPrinter.cpp

R600/SI: Use correct dest register class for V_READFIRSTLANE_B32

2014-03-17 17:03:51 +00:00

AMDGPUAsmPrinter.h

…

AMDGPUCallingConv.td

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AMDGPUConvertToISA.cpp

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AMDGPUFrameLowering.cpp

…

AMDGPUFrameLowering.h

…

AMDGPUInstrInfo.cpp

Fix indentation

2014-03-11 00:01:27 +00:00

AMDGPUInstrInfo.h

…

AMDGPUInstrInfo.td

R600: Match sign_extend_inreg to BFE instructions

2014-03-17 18:58:11 +00:00

AMDGPUInstructions.td

R600: Reorganize tablegen instruction definitions

2014-03-24 16:07:25 +00:00

AMDGPUIntrinsics.td

…

AMDGPUISelDAGToDAG.cpp

[Modules] Move ValueMap to the IR library. While this class does not

2014-03-04 11:26:31 +00:00

AMDGPUISelLowering.cpp

R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp

2014-03-25 18:18:27 +00:00

AMDGPUISelLowering.h

R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp

2014-03-25 18:18:27 +00:00

AMDGPUMachineFunction.cpp

…

AMDGPUMachineFunction.h

…

AMDGPUMCInstLower.cpp

R600: Verify all instructions in the AsmPrinter on debug builds

2014-02-28 21:36:41 +00:00

AMDGPUMCInstLower.h

…

AMDGPURegisterInfo.cpp

…

AMDGPURegisterInfo.h

…

AMDGPURegisterInfo.td

…

AMDGPUSubtarget.cpp

…

AMDGPUSubtarget.h

R600: Match sign_extend_inreg to BFE instructions

2014-03-17 18:58:11 +00:00

AMDGPUTargetMachine.cpp

R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()

2014-03-21 15:51:57 +00:00

AMDGPUTargetMachine.h

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AMDGPUTargetTransformInfo.cpp

[TTI] There is actually no realistic way to pop TTI implementations off

2014-03-10 02:45:14 +00:00

AMDILBase.td

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AMDILCFGStructurizer.cpp

R600: Don't viewCFG() under DEBUG() except on failure.

2014-03-24 20:29:02 +00:00

AMDILInstrInfo.td

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AMDILIntrinsicInfo.cpp

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AMDILIntrinsicInfo.h

…

AMDILIntrinsics.td

R600: Match sign_extend_inreg to BFE instructions

2014-03-17 18:58:11 +00:00

AMDILISelLowering.cpp

R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cpp

2014-03-25 18:18:27 +00:00

AMDILRegisterInfo.td

…

CaymanInstructions.td

R600: Reorganize tablegen instruction definitions

2014-03-24 16:07:25 +00:00

CMakeLists.txt

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EvergreenInstructions.td

R600: Reorganize tablegen instruction definitions

2014-03-24 16:07:25 +00:00

LLVMBuild.txt

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Makefile

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Processors.td

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R600ClauseMergePass.cpp

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R600ControlFlowFinalizer.cpp

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R600Defines.h

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R600EmitClauseMarkers.cpp

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R600ExpandSpecialInstrs.cpp

[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.

2014-03-02 12:27:27 +00:00

R600InstrFormats.td

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R600InstrInfo.cpp

[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.

2014-03-02 12:27:27 +00:00

R600InstrInfo.h

…

R600Instructions.td

R600: Reorganize tablegen instruction definitions

2014-03-24 16:07:25 +00:00

R600Intrinsics.td

…

R600ISelLowering.cpp

R600: Match sign_extend_inreg to BFE instructions

2014-03-17 18:58:11 +00:00

R600ISelLowering.h

…

R600MachineFunctionInfo.cpp

…

R600MachineFunctionInfo.h

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R600MachineScheduler.cpp

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R600MachineScheduler.h

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R600OptimizeVectorRegisters.cpp

Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing

2014-03-13 23:12:04 +00:00

R600Packetizer.cpp

[C++11] Replace llvm::next and llvm::prior with std::next and std::prev.

2014-03-02 12:27:27 +00:00

R600RegisterInfo.cpp

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R600RegisterInfo.h

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R600RegisterInfo.td

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R600Schedule.td

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R600TextureIntrinsicsReplacer.cpp

[Layering] Move InstVisitor.h into the IR library as it is pretty

2014-03-06 03:23:41 +00:00

R700Instructions.td

R600: Reorganize tablegen instruction definitions

2014-03-24 16:07:25 +00:00

SIAnnotateControlFlow.cpp

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SIDefines.h

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SIFixSGPRCopies.cpp

Phase 2 of the great MachineRegisterInfo cleanup. This time, we're changing

2014-03-13 23:12:04 +00:00

SIInsertWaits.cpp

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SIInstrFormats.td

R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()

2014-03-21 15:51:57 +00:00

SIInstrInfo.cpp

R600/SI: Fix extra mov from legalizing 64-bit SALU ops.

2014-03-24 20:08:13 +00:00

SIInstrInfo.h

R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.

2014-03-24 20:08:09 +00:00

SIInstrInfo.td

R600/SI: Add unused LDS 2 form instructions.

2014-03-19 22:19:56 +00:00

SIInstructions.td

R600/SI: Fix 64-bit bit ops that require the VALU.

2014-03-24 20:08:05 +00:00

SIIntrinsics.td

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SIISelLowering.cpp

R600/SI: Fix 64-bit private loads.

2014-03-24 17:50:46 +00:00

SIISelLowering.h

R600/SI: Custom select 64-bit ADD

2014-02-25 21:36:18 +00:00

SILowerControlFlow.cpp

R600/SI: Use correct dest register class for V_READFIRSTLANE_B32

2014-03-17 17:03:51 +00:00

SIMachineFunctionInfo.cpp

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SIMachineFunctionInfo.h

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SIRegisterInfo.cpp

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SIRegisterInfo.h

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SIRegisterInfo.td

R600/SI: Use correct dest register class for V_READFIRSTLANE_B32

2014-03-17 17:03:51 +00:00

SISchedule.td

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SITypeRewriter.cpp

[Layering] Move InstVisitor.h into the IR library as it is pretty

2014-03-06 03:23:41 +00:00