llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-19 03:29:22 +00:00

History

Evan Cheng 6e141fd048 Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8		2007-12-12 23:12:09 +00:00
..
Alpha.h	Add all that branch mangling niftiness	2006-10-31 16:49:55 +00:00
Alpha.td	For PR1336:	2007-04-16 14:06:19 +00:00
AlphaAsmPrinter.cpp	Eliminate the remaining uses of getTypeSize. This	2007-11-05 00:04:43 +00:00
AlphaBranchSelector.cpp	Drop 'const'	2007-05-03 01:11:54 +00:00
AlphaCodeEmitter.cpp	Drop 'const'	2007-05-03 01:11:54 +00:00
AlphaInstrFormats.td	No more noResults.	2007-07-21 00:34:19 +00:00
AlphaInstrInfo.cpp	Add lengthof and endof templates that hide a lot of sizeof computations.	2007-09-07 04:06:50 +00:00
AlphaInstrInfo.h	RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.	2007-05-18 00:05:48 +00:00
AlphaInstrInfo.td	Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled.	2007-12-12 23:12:09 +00:00
AlphaISelDAGToDAG.cpp	Enhance APFloat to retain bits of NaNs (fixes oggenc).	2007-08-31 04:03:46 +00:00
AlphaISelLowering.cpp	Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stack	2007-11-13 00:44:25 +00:00
AlphaISelLowering.h	More explicit keywords.	2007-08-02 21:21:54 +00:00
AlphaJITInfo.cpp	What should be the last unnecessary <iostream>s in the library.	2006-12-07 22:21:48 +00:00
AlphaJITInfo.h	Completely rearchitect the interface between targets and the pass manager.	2006-09-04 04:14:57 +00:00
AlphaLLRP.cpp	Drop 'const'	2007-05-03 01:11:54 +00:00
AlphaRegisterInfo.cpp	Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether	2007-12-05 03:14:33 +00:00
AlphaRegisterInfo.h	Add a argument to storeRegToStackSlot and storeRegToAddr to specify whether	2007-12-05 03:14:33 +00:00
AlphaRegisterInfo.td	Use TableGen to emit information for dwarf register numbers.	2007-11-11 19:50:10 +00:00
AlphaRelocations.h	Patches to make the LLVM sources more -pedantic clean. Patch provided	2006-05-24 17:04:05 +00:00
AlphaSchedule.td	Alpha Scheduling classes	2006-03-09 17:16:45 +00:00
AlphaSubtarget.cpp	FTOIT and ITOFT are bit converts, and if we drop 21264s, are always available	2007-01-24 21:09:16 +00:00
AlphaSubtarget.h	FTOIT and ITOFT are bit converts, and if we drop 21264s, are always available	2007-01-24 21:09:16 +00:00
AlphaTargetAsmInfo.cpp	Simplify a bit	2006-12-07 23:55:55 +00:00
AlphaTargetAsmInfo.h	More explicit keywords.	2007-09-25 20:27:06 +00:00
AlphaTargetMachine.cpp	long double patch 2 of N. Handle it in TargetData.	2007-08-03 20:20:50 +00:00
AlphaTargetMachine.h	Added -print-emitted-asm to print out JIT generated asm to cerr.	2007-07-20 21:56:13 +00:00
Makefile	Autogen subtarget information from .td files.	2005-10-23 22:15:34 +00:00
README.txt	Readme	2007-03-31 15:05:44 +00:00

README.txt

***

add gcc builtins for alpha instructions


***

custom expand byteswap into nifty 
extract/insert/mask byte/word/longword/quadword low/high
sequences

***

see if any of the extract/insert/mask operations can be added

***

match more interesting things for cmovlbc cmovlbs (move if low bit clear/set)

***

lower srem and urem

remq(i,j):  i - (j * divq(i,j)) if j != 0
remqu(i,j): i - (j * divqu(i,j)) if j != 0
reml(i,j):  i - (j * divl(i,j)) if j != 0
remlu(i,j): i - (j * divlu(i,j)) if j != 0

***

add crazy vector instructions (MVI):

(MIN|MAX)(U|S)(B8|W4) min and max, signed and unsigned, byte and word
PKWB, UNPKBW pack/unpack word to byte
PKLB UNPKBL pack/unpack long to byte
PERR pixel error (sum accross bytes of bytewise abs(i8v8 a - i8v8 b))

cmpbytes bytewise cmpeq of i8v8 a and i8v8 b (not part of MVI extentions)

this has some good examples for other operations that can be synthesised well 
from these rather meager vector ops (such as saturating add).
http://www.alphalinux.org/docs/MVI-full.html