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https://github.com/c64scene-ar/llvm-6502.git
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e729f0f935
Use VGPR_32 register class instead. These two register classes were identical and having separate classes was causing SIInstrInfo::isLegalOperands() to be overly conservative in some cases. This change is necessary to prevent future paches from missing a folding opportunity in fneg-fabs.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225382 91177308-0d34-0410-b5e6-96231b3b80d8
90 lines
2.8 KiB
TableGen
90 lines
2.8 KiB
TableGen
//===-- VIInstructions.td - VI Instruction Defintions ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Instruction definitions for VI and newer.
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//===----------------------------------------------------------------------===//
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let SubtargetPredicate = isVI in {
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def V_LDEXP_F32 : VOP3InstVI <0x288, "v_ldexp_f32", VOP_F32_F32_I32,
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AMDGPUldexp
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>;
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def V_BFM_B32 : VOP3InstVI <0x293, "v_bfm_b32", VOP_I32_I32_I32, AMDGPUbfm>;
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def V_BCNT_U32_B32 : VOP3InstVI <0x28b, "v_bcnt_u32_b32", VOP_I32_I32_I32>;
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def V_MBCNT_LO_U32_B32 : VOP3InstVI <0x28c, "v_mbcnt_lo_u32_b32",
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VOP_I32_I32_I32
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>;
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def V_MBCNT_HI_U32_B32 : VOP3InstVI <0x28d, "v_mbcnt_hi_u32_b32",
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VOP_I32_I32_I32
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>;
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def V_CVT_PKRTZ_F16_F32 : VOP3InstVI <0x296, "v_cvt_pkrtz_f16_f32",
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VOP_I32_F32_F32, int_SI_packf16
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>;
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defm BUFFER_LOAD_DWORD_VI : MUBUF_Load_Helper_vi <
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0x14, "buffer_load_dword", VGPR_32, i32, global_load
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>;
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defm BUFFER_LOAD_FORMAT_XYZW_VI : MUBUF_Load_Helper_vi <
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0x03, "buffer_load_format_xyzw", VReg_128
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>;
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} // End SubtargetPredicate = isVI
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//===----------------------------------------------------------------------===//
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// VOP2 Patterns
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//===----------------------------------------------------------------------===//
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let Predicates = [isVI] in {
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def : Pat <
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(int_SI_tid),
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(V_MBCNT_HI_U32_B32 0xffffffff,
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(V_MBCNT_LO_U32_B32 0xffffffff, 0))
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>;
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//===----------------------------------------------------------------------===//
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// SMEM Patterns
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//===----------------------------------------------------------------------===//
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// 1. Offset as 8bit DWORD immediate
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def : Pat <
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(SIload_constant v4i32:$sbase, IMM20bit:$offset),
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(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_i32imm $offset))
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>;
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//===----------------------------------------------------------------------===//
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// MUBUF Patterns
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//===----------------------------------------------------------------------===//
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// Offset in an 32Bit VGPR
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def : Pat <
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(SIload_constant v4i32:$sbase, i32:$voff),
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(BUFFER_LOAD_DWORD_VI_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
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>;
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// Offset in an 32Bit VGPR
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def : Pat <
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(SIload_constant v4i32:$sbase, i32:$voff),
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(BUFFER_LOAD_DWORD_VI_OFFEN $sbase, $voff, 0, 0, 0, 0, 0)
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>;
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/* int_SI_vs_load_input */
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def : Pat<
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(SIload_input v4i32:$tlst, imm:$attr_offset, i32:$buf_idx_vgpr),
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(BUFFER_LOAD_FORMAT_XYZW_VI_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0)
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>;
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defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_VI_OFFSET,
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BUFFER_LOAD_DWORD_VI_OFFEN,
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BUFFER_LOAD_DWORD_VI_IDXEN,
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BUFFER_LOAD_DWORD_VI_BOTHEN>;
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} // End Predicates = [isVI]
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