mirror of
https://github.com/c64scene-ar/llvm-6502.git
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26d628d6ce
Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230775 91177308-0d34-0410-b5e6-96231b3b80d8
138 lines
3.6 KiB
LLVM
138 lines
3.6 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
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; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7
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; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
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; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
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; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6
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; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6
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; RUN: llc < %s -O0 -fast-isel-abort=1 -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7
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; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports
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; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always
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; using two shifts.
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; Note that lsl, asr and lsr in Thumb are all encoded as 16-bit instructions
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; and therefore must set flags. {{s?}} below denotes this, instead of
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; duplicating tests.
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; zext
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define i8 @zext_1_8(i1 %a) nounwind ssp {
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; v7-LABEL: zext_1_8:
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; v7: and r0, r0, #1
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; prev6-LABEL: zext_1_8:
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; prev6: and r0, r0, #1
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%r = zext i1 %a to i8
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ret i8 %r
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}
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define i16 @zext_1_16(i1 %a) nounwind ssp {
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; v7-LABEL: zext_1_16:
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; v7: and r0, r0, #1
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; prev6-LABEL: zext_1_16:
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; prev6: and r0, r0, #1
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%r = zext i1 %a to i16
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ret i16 %r
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}
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define i32 @zext_1_32(i1 %a) nounwind ssp {
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; v7-LABEL: zext_1_32:
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; v7: and r0, r0, #1
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; prev6-LABEL: zext_1_32:
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; prev6: and r0, r0, #1
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%r = zext i1 %a to i32
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ret i32 %r
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}
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define i16 @zext_8_16(i8 %a) nounwind ssp {
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; v7-LABEL: zext_8_16:
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; v7: and r0, r0, #255
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; prev6-LABEL: zext_8_16:
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; prev6: and r0, r0, #255
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%r = zext i8 %a to i16
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ret i16 %r
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}
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define i32 @zext_8_32(i8 %a) nounwind ssp {
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; v7-LABEL: zext_8_32:
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; v7: and r0, r0, #255
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; prev6-LABEL: zext_8_32:
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; prev6: and r0, r0, #255
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%r = zext i8 %a to i32
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ret i32 %r
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}
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define i32 @zext_16_32(i16 %a) nounwind ssp {
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; v7-LABEL: zext_16_32:
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; v7: uxth r0, r0
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; prev6-LABEL: zext_16_32:
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; prev6: lsl{{s?}} r0, r0, #16
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; prev6: lsr{{s?}} r0, r0, #16
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%r = zext i16 %a to i32
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ret i32 %r
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}
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; sext
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define i8 @sext_1_8(i1 %a) nounwind ssp {
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; v7-LABEL: sext_1_8:
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; v7: lsl{{s?}} r0, r0, #31
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; v7: asr{{s?}} r0, r0, #31
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; prev6-LABEL: sext_1_8:
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; prev6: lsl{{s?}} r0, r0, #31
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; prev6: asr{{s?}} r0, r0, #31
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%r = sext i1 %a to i8
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ret i8 %r
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}
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define i16 @sext_1_16(i1 %a) nounwind ssp {
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; v7-LABEL: sext_1_16:
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; v7: lsl{{s?}} r0, r0, #31
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; v7: asr{{s?}} r0, r0, #31
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; prev6-LABEL: sext_1_16:
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; prev6: lsl{{s?}} r0, r0, #31
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; prev6: asr{{s?}} r0, r0, #31
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%r = sext i1 %a to i16
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ret i16 %r
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}
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define i32 @sext_1_32(i1 %a) nounwind ssp {
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; v7-LABEL: sext_1_32:
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; v7: lsl{{s?}} r0, r0, #31
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; v7: asr{{s?}} r0, r0, #31
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; prev6-LABEL: sext_1_32:
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; prev6: lsl{{s?}} r0, r0, #31
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; prev6: asr{{s?}} r0, r0, #31
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%r = sext i1 %a to i32
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ret i32 %r
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}
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define i16 @sext_8_16(i8 %a) nounwind ssp {
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; v7-LABEL: sext_8_16:
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; v7: sxtb r0, r0
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; prev6-LABEL: sext_8_16:
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; prev6: lsl{{s?}} r0, r0, #24
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; prev6: asr{{s?}} r0, r0, #24
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%r = sext i8 %a to i16
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ret i16 %r
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}
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define i32 @sext_8_32(i8 %a) nounwind ssp {
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; v7-LABEL: sext_8_32:
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; v7: sxtb r0, r0
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; prev6-LABEL: sext_8_32:
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; prev6: lsl{{s?}} r0, r0, #24
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; prev6: asr{{s?}} r0, r0, #24
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%r = sext i8 %a to i32
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ret i32 %r
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}
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define i32 @sext_16_32(i16 %a) nounwind ssp {
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; v7-LABEL: sext_16_32:
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; v7: sxth r0, r0
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; prev6-LABEL: sext_16_32:
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; prev6: lsl{{s?}} r0, r0, #16
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; prev6: asr{{s?}} r0, r0, #16
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%r = sext i16 %a to i32
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ret i32 %r
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}
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