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Currently we have such types as legal vector types. The DAG combiner may generate some DAG nodes having such types but we don't have patterns to match them. E.g. a load i32 and a bitcast i32 to v1i32 will be combined into a load v1i32: bitcast (load i32) to v1i32 -> load v1i32. So this patch fixes such problems for load/dup instructions. If v1i8/v1i16/v1i32 are not legal any more, the code in this patch can be deleted. So I also add some FIXME. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197361 91177308-0d34-0410-b5e6-96231b3b80d8 |
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