Hal Finkel 56d926ac14 Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructions ... Like the addi/addis instructions themselves, these pseudo instructions also cannot have r0 as their register parameter (because it will be interpreted as the value 0). This is not yet testable because we don't yet allocate r0 (and even when we do, any regression test would be very fragile because it would depend on the register allocator heuristics). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178118 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-27 05:57:56 +00:00
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Analysis	BasicAA: Only query twice if the result of the more general query was MayAlias	2013-03-26 18:07:53 +00:00
Archive
AsmParser
Bitcode
CodeGen	Fix the register scavenger for targets that provide custom spilling	2013-03-26 21:20:15 +00:00
DebugInfo
ExecutionEngine
IR	Adding DIImportedModules to DIScopes.	2013-03-27 00:07:26 +00:00
IRReader	Split out the IRReader header and the utility functions it provides into	2013-03-26 02:25:37 +00:00
Linker
MC
Object
Option
Support	Add a boolean parameter to the ExecuteAndWait static function to indicated	2013-03-26 23:35:00 +00:00
TableGen
Target	Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructions	2013-03-27 05:57:56 +00:00
Transforms	Use the full path when outputting the `.gcda' file.	2013-03-26 22:47:50 +00:00
CMakeLists.txt	Split out the IRReader header and the utility functions it provides into	2013-03-26 02:25:37 +00:00
LLVMBuild.txt	Split out the IRReader header and the utility functions it provides into	2013-03-26 02:25:37 +00:00
Makefile	Split out the IRReader header and the utility functions it provides into	2013-03-26 02:25:37 +00:00