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The change in SelectionDAGBuilder is needed to allow using bitcasts to convert between f64 (the default type for ARM "d" registers) and 64-bit Neon vector types. Radar 7457110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91649 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
736 B
LLVM
26 lines
736 B
LLVM
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
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; Radar 7449043
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%struct.int32x4_t = type { <4 x i32> }
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define arm_apcscc void @t() nounwind {
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entry:
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; CHECK: vmov.I64 q15, #0
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; CHECK: vmov.32 d30[0], r0
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; CHECK: vmov q0, q15
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%tmp = alloca %struct.int32x4_t, align 16
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call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind
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ret void
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}
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; Radar 7457110
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%struct.int32x2_t = type { <4 x i32> }
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define arm_apcscc void @t2() nounwind {
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entry:
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; CHECK: vmov d30, d0
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; CHECK: vmov.32 r0, d30[0]
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%asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind
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ret void
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}
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