Michel Danzer cf4061a601 R600/SI: Add pattern for zero-extending i1 to i32 ... Fixes opencl-example if_* tests with radeonsi. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74469 Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200830 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-05 09:48:05 +00:00
..
AArch64	ARM & AArch64: merge NEON absolute compare intrinsics	2014-02-04 14:55:42 +00:00
ARM	Fix PR18345: ldr= pseudo instruction produces incorrect code when using in inline assembly	2014-02-04 17:22:40 +00:00
CPP
Generic	Additional fix for 200201: due to dependence on bitwidth test was moved to X86 directory.	2014-01-27 09:43:10 +00:00
Hexagon	DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer emits zero-length arrays as {i32 0}	2014-02-04 01:23:52 +00:00
Inputs
Mips	[mips][msa] Add insert.d instruction.	2014-01-31 13:31:20 +00:00
MSP430
NVPTX	[NVPTX] Fix emitting aggregate parameters	2014-01-28 18:35:29 +00:00
PowerPC	DebugInfo: Remove some unneeded conditionals now that DIBuilder no longer emits zero-length arrays as {i32 0}	2014-02-04 01:23:52 +00:00
R600	R600/SI: Add pattern for zero-extending i1 to i32	2014-02-05 09:48:05 +00:00
SPARC	[Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly.	2014-02-01 18:54:16 +00:00
SystemZ	XFAIL test/CodeGen/SystemZ/alias-01.ll which requires CodeGen TBAA	2014-01-25 19:31:44 +00:00
Thumb
Thumb2	PGO branch weight: update edge weights in IfConverter.	2014-01-29 23:18:47 +00:00
X86	AVX-512: Added intrinsic for cvtph2ps.	2014-02-05 07:05:03 +00:00
XCore