Justin Holewinski 5a3cb924c6 PTX: support for bitwise operations on predicates ... - selection of bitwise preds (AND, OR, XOR) - new bitwise.ll test Patch by Dan Bailey git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130353 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-28 00:19:51 +00:00
..
Alpha	If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.	2010-12-06 22:39:26 +00:00
ARM	If converter was being too cute. It look for root BBs (which don't have	2011-04-27 19:32:43 +00:00
Blackfin	Don't completely eliminate identity copies that also modify super register liveness.	2011-03-31 17:55:25 +00:00
CBackend
CellSPU	don't test for codegen of 'store undef'	2011-04-09 02:31:26 +00:00
CPP
Generic	Un-XFAIL this test for ARM. <rdar://problem/7662569>	2011-04-20 21:47:45 +00:00
MBlaze	Add scheduling information for the MBlaze backend.	2011-04-11 22:31:52 +00:00
Mips	Lower BlockAddress node when relocation-model is static.	2011-04-25 17:10:45 +00:00
MSP430	Enhance ComputeMaskedBits to know that aligned frameindexes	2011-02-13 22:25:43 +00:00
PowerPC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
PTX	PTX: support for bitwise operations on predicates	2011-04-28 00:19:51 +00:00
SPARC	These tests no longer require linear scan because reserved register coalescing is now universal.	2011-04-05 21:40:41 +00:00
SystemZ	Fix SystemZ tests	2011-03-31 23:02:12 +00:00
Thumb	Be careful about scheduling nodes above previous calls. It increase usages of	2011-04-26 21:31:35 +00:00
Thumb2	Be careful about scheduling nodes above previous calls. It increase usages of	2011-04-26 21:31:35 +00:00
X86	fast-isel sret. We actually don't need to do anything special on x86. :) rdar://problem/9303592 .	2011-04-27 23:58:52 +00:00
XCore	Fix Mips, Sparc, and XCore tests that were dependent on register allocation.	2011-03-31 18:42:43 +00:00