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only concrete implementation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@13977 91177308-0d34-0410-b5e6-96231b3b80d8
188 lines
7.1 KiB
C++
188 lines
7.1 KiB
C++
//===-- PhyRegAlloc.h - Graph Coloring Register Allocator -------*- c++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is the main entry point for register allocation.
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//
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// Notes:
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// * RegisterClasses: Each RegClass accepts a
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// TargetRegClass which contains machine specific info about that register
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// class. The code in the RegClass is machine independent and they use
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// access functions in the TargetRegClass object passed into it to get
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// machine specific info.
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//
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// * Machine dependent work: All parts of the register coloring algorithm
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// except coloring of an individual node are machine independent.
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//
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//===----------------------------------------------------------------------===//
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#ifndef PHYREGALLOC_H
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#define PHYREGALLOC_H
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#include "LiveRangeInfo.h"
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#include "llvm/Pass.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/Target/TargetMachine.h"
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#include "../SparcV9RegInfo.h"
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#include <map>
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namespace llvm {
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class MachineFunction;
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class FunctionLiveVarInfo;
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class MachineInstr;
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class LoopInfo;
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class RegClass;
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class Constant;
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//----------------------------------------------------------------------------
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// Class AddedInstrns:
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// When register allocator inserts new instructions in to the existing
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// instruction stream, it does NOT directly modify the instruction stream.
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// Rather, it creates an object of AddedInstrns and stick it in the
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// AddedInstrMap for an existing instruction. This class contains two vectors
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// to store such instructions added before and after an existing instruction.
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//----------------------------------------------------------------------------
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struct AddedInstrns {
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std::vector<MachineInstr*> InstrnsBefore;//Insts added BEFORE an existing inst
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std::vector<MachineInstr*> InstrnsAfter; //Insts added AFTER an existing inst
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inline void clear () { InstrnsBefore.clear (); InstrnsAfter.clear (); }
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};
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//----------------------------------------------------------------------------
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// class PhyRegAlloc:
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// Main class the register allocator. Call runOnFunction() to allocate
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// registers for a Function.
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//----------------------------------------------------------------------------
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class PhyRegAlloc : public FunctionPass {
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std::vector<RegClass *> RegClassList; // vector of register classes
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const TargetMachine &TM; // target machine
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const Function *Fn; // name of the function we work on
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MachineFunction *MF; // descriptor for method's native code
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FunctionLiveVarInfo *LVI; // LV information for this method
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// (already computed for BBs)
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LiveRangeInfo *LRI; // LR info (will be computed)
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const SparcV9RegInfo &MRI; // Machine Register information
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const unsigned NumOfRegClasses; // recorded here for efficiency
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// Map to indicate whether operands of each MachineInstr have been
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// updated according to their assigned colors. This is only used in
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// assertion checking (debug builds).
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std::map<const MachineInstr *, bool> OperandsColoredMap;
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// AddedInstrMap - Used to store instrns added in this phase
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std::map<const MachineInstr *, AddedInstrns> AddedInstrMap;
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// ScratchRegsUsed - Contains scratch register uses for a particular MI.
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typedef std::multimap<const MachineInstr*, int> ScratchRegsUsedTy;
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ScratchRegsUsedTy ScratchRegsUsed;
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AddedInstrns AddedInstrAtEntry; // to store instrns added at entry
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const LoopInfo *LoopDepthCalc; // to calculate loop depths
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PhyRegAlloc(const PhyRegAlloc&); // DO NOT IMPLEMENT
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void operator=(const PhyRegAlloc&); // DO NOT IMPLEMENT
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public:
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typedef std::map<const Function *, std::vector<AllocInfo> > SavedStateMapTy;
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inline PhyRegAlloc (const TargetMachine &TM_) :
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TM (TM_), MRI (*TM.getRegInfo ()),
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NumOfRegClasses (MRI.getNumOfRegClasses ()) { }
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virtual ~PhyRegAlloc() { }
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/// runOnFunction - Main method called for allocating registers.
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///
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virtual bool runOnFunction (Function &F);
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virtual bool doFinalization (Module &M);
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virtual void getAnalysisUsage (AnalysisUsage &AU) const;
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const char *getPassName () const {
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return "Traditional graph-coloring reg. allocator";
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}
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inline const RegClass* getRegClassByID(unsigned id) const {
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return RegClassList[id];
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}
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inline RegClass *getRegClassByID(unsigned id) { return RegClassList[id]; }
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private:
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SavedStateMapTy FnAllocState;
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void addInterference(const Value *Def, const ValueSet *LVSet,
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bool isCallInst);
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bool markAllocatedRegs(MachineInstr* MInst);
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void addInterferencesForArgs();
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void createIGNodeListsAndIGs();
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void buildInterferenceGraphs();
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void saveStateForValue (std::vector<AllocInfo> &state,
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const Value *V, int Insn, int Opnd);
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void saveState();
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void dumpSavedState();
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void finishSavingState(Module &M);
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void setCallInterferences(const MachineInstr *MI,
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const ValueSet *LVSetAft);
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void move2DelayedInstr(const MachineInstr *OrigMI,
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const MachineInstr *DelayedMI);
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void markUnusableSugColors();
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void allocateStackSpace4SpilledLRs();
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void insertCode4SpilledLR(const LiveRange *LR,
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MachineBasicBlock::iterator& MII,
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MachineBasicBlock &MBB, unsigned OpNum);
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/// Method for inserting caller saving code. The caller must save all the
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/// volatile registers live across a call.
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///
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void insertCallerSavingCode(std::vector<MachineInstr*>& instrnsBefore,
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std::vector<MachineInstr*>& instrnsAfter,
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MachineInstr *CallMI,
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const BasicBlock *BB);
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void colorIncomingArgs();
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void colorCallRetArgs();
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void updateMachineCode();
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void updateInstruction(MachineBasicBlock::iterator& MII,
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MachineBasicBlock &MBB);
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int getUsableUniRegAtMI(int RegType, const ValueSet *LVSetBef,
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MachineInstr *MI,
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std::vector<MachineInstr*>& MIBef,
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std::vector<MachineInstr*>& MIAft);
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/// Callback method used to find unused registers.
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/// LVSetBef is the live variable set to search for an unused register.
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/// If it is not specified, the LV set before the current MI is used.
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/// This is sufficient as long as no new copy instructions are generated
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/// to copy the free register to memory.
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///
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int getUnusedUniRegAtMI(RegClass *RC, int RegType,
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const MachineInstr *MI,
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const ValueSet *LVSetBef = 0);
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void setRelRegsUsedByThisInst(RegClass *RC, int RegType,
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const MachineInstr *MI);
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int getUniRegNotUsedByThisInst(RegClass *RC, int RegType,
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const MachineInstr *MI);
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void addInterf4PseudoInstr(const MachineInstr *MI);
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};
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} // End llvm namespace
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#endif
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