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Add an assertion to linear scan to prevent it from allocating registers outside the register class. <rdar://problem/9183021> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128254 91177308-0d34-0410-b5e6-96231b3b80d8
1253 lines
40 KiB
C++
1253 lines
40 KiB
C++
//===- ARMBaseRegisterInfo.cpp - ARM Register Information -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the base ARM implementation of TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMBaseRegisterInfo.h"
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#include "ARMFrameLowering.h"
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#include "ARMInstrInfo.h"
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#include "ARMMachineFunctionInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/LLVMContext.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineLocation.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/CommandLine.h"
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using namespace llvm;
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static cl::opt<bool>
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ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
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cl::desc("Force use of virtual base registers for stack load/store"));
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static cl::opt<bool>
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EnableLocalStackAlloc("enable-local-stack-alloc", cl::init(true), cl::Hidden,
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cl::desc("Enable pre-regalloc stack frame index allocation"));
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static cl::opt<bool>
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EnableBasePointer("arm-use-base-pointer", cl::Hidden, cl::init(true),
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cl::desc("Enable use of a base pointer for complex stack frames"));
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ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
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const ARMSubtarget &sti)
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: ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
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TII(tii), STI(sti),
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FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
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BasePtr(ARM::R6) {
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}
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const unsigned*
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ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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static const unsigned CalleeSavedRegs[] = {
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ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
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ARM::R7, ARM::R6, ARM::R5, ARM::R4,
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ARM::D15, ARM::D14, ARM::D13, ARM::D12,
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ARM::D11, ARM::D10, ARM::D9, ARM::D8,
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0
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};
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static const unsigned DarwinCalleeSavedRegs[] = {
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// Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
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// register.
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ARM::LR, ARM::R7, ARM::R6, ARM::R5, ARM::R4,
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ARM::R11, ARM::R10, ARM::R8,
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ARM::D15, ARM::D14, ARM::D13, ARM::D12,
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ARM::D11, ARM::D10, ARM::D9, ARM::D8,
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0
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};
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return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
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}
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BitVector ARMBaseRegisterInfo::
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getReservedRegs(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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// FIXME: avoid re-calculating this everytime.
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BitVector Reserved(getNumRegs());
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Reserved.set(ARM::SP);
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Reserved.set(ARM::PC);
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Reserved.set(ARM::FPSCR);
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if (TFI->hasFP(MF))
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Reserved.set(FramePtr);
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if (hasBasePointer(MF))
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Reserved.set(BasePtr);
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// Some targets reserve R9.
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if (STI.isR9Reserved())
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Reserved.set(ARM::R9);
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return Reserved;
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}
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bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF,
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unsigned Reg) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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switch (Reg) {
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default: break;
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case ARM::SP:
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case ARM::PC:
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return true;
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case ARM::R6:
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if (hasBasePointer(MF))
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return true;
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break;
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case ARM::R7:
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case ARM::R11:
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if (FramePtr == Reg && TFI->hasFP(MF))
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return true;
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break;
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case ARM::R9:
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return STI.isR9Reserved();
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}
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return false;
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}
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const TargetRegisterClass *
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ARMBaseRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
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const TargetRegisterClass *B,
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unsigned SubIdx) const {
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switch (SubIdx) {
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default: return 0;
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case ARM::ssub_0:
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case ARM::ssub_1:
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case ARM::ssub_2:
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case ARM::ssub_3: {
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// S sub-registers.
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if (A->getSize() == 8) {
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if (B == &ARM::SPR_8RegClass)
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return &ARM::DPR_8RegClass;
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assert(B == &ARM::SPRRegClass && "Expecting SPR register class!");
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if (A == &ARM::DPR_8RegClass)
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return A;
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return &ARM::DPR_VFP2RegClass;
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}
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if (A->getSize() == 16) {
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if (B == &ARM::SPR_8RegClass)
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return &ARM::QPR_8RegClass;
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return &ARM::QPR_VFP2RegClass;
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}
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if (A->getSize() == 32) {
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if (B == &ARM::SPR_8RegClass)
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return 0; // Do not allow coalescing!
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return &ARM::QQPR_VFP2RegClass;
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}
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assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
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return 0; // Do not allow coalescing!
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}
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case ARM::dsub_0:
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case ARM::dsub_1:
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case ARM::dsub_2:
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case ARM::dsub_3: {
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// D sub-registers.
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if (A->getSize() == 16) {
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if (B == &ARM::DPR_VFP2RegClass)
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return &ARM::QPR_VFP2RegClass;
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if (B == &ARM::DPR_8RegClass)
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return 0; // Do not allow coalescing!
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return A;
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}
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if (A->getSize() == 32) {
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if (B == &ARM::DPR_VFP2RegClass)
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return &ARM::QQPR_VFP2RegClass;
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if (B == &ARM::DPR_8RegClass)
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return 0; // Do not allow coalescing!
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return A;
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}
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assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
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if (B != &ARM::DPRRegClass)
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return 0; // Do not allow coalescing!
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return A;
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}
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case ARM::dsub_4:
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case ARM::dsub_5:
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case ARM::dsub_6:
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case ARM::dsub_7: {
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// D sub-registers of QQQQ registers.
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if (A->getSize() == 64 && B == &ARM::DPRRegClass)
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return A;
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return 0; // Do not allow coalescing!
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}
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case ARM::qsub_0:
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case ARM::qsub_1: {
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// Q sub-registers.
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if (A->getSize() == 32) {
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if (B == &ARM::QPR_VFP2RegClass)
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return &ARM::QQPR_VFP2RegClass;
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if (B == &ARM::QPR_8RegClass)
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return 0; // Do not allow coalescing!
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return A;
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}
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assert(A->getSize() == 64 && "Expecting a QQQQ register class!");
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if (B == &ARM::QPRRegClass)
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return A;
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return 0; // Do not allow coalescing!
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}
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case ARM::qsub_2:
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case ARM::qsub_3: {
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// Q sub-registers of QQQQ registers.
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if (A->getSize() == 64 && B == &ARM::QPRRegClass)
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return A;
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return 0; // Do not allow coalescing!
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}
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}
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return 0;
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}
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bool
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ARMBaseRegisterInfo::canCombineSubRegIndices(const TargetRegisterClass *RC,
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SmallVectorImpl<unsigned> &SubIndices,
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unsigned &NewSubIdx) const {
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unsigned Size = RC->getSize() * 8;
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if (Size < 6)
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return 0;
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NewSubIdx = 0; // Whole register.
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unsigned NumRegs = SubIndices.size();
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if (NumRegs == 8) {
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// 8 D registers -> 1 QQQQ register.
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return (Size == 512 &&
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SubIndices[0] == ARM::dsub_0 &&
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SubIndices[1] == ARM::dsub_1 &&
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SubIndices[2] == ARM::dsub_2 &&
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SubIndices[3] == ARM::dsub_3 &&
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SubIndices[4] == ARM::dsub_4 &&
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SubIndices[5] == ARM::dsub_5 &&
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SubIndices[6] == ARM::dsub_6 &&
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SubIndices[7] == ARM::dsub_7);
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} else if (NumRegs == 4) {
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if (SubIndices[0] == ARM::qsub_0) {
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// 4 Q registers -> 1 QQQQ register.
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return (Size == 512 &&
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SubIndices[1] == ARM::qsub_1 &&
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SubIndices[2] == ARM::qsub_2 &&
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SubIndices[3] == ARM::qsub_3);
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} else if (SubIndices[0] == ARM::dsub_0) {
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// 4 D registers -> 1 QQ register.
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if (Size >= 256 &&
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SubIndices[1] == ARM::dsub_1 &&
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SubIndices[2] == ARM::dsub_2 &&
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SubIndices[3] == ARM::dsub_3) {
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if (Size == 512)
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NewSubIdx = ARM::qqsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::dsub_4) {
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// 4 D registers -> 1 QQ register (2nd).
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if (Size == 512 &&
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SubIndices[1] == ARM::dsub_5 &&
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SubIndices[2] == ARM::dsub_6 &&
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SubIndices[3] == ARM::dsub_7) {
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NewSubIdx = ARM::qqsub_1;
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return true;
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}
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} else if (SubIndices[0] == ARM::ssub_0) {
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// 4 S registers -> 1 Q register.
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if (Size >= 128 &&
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SubIndices[1] == ARM::ssub_1 &&
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SubIndices[2] == ARM::ssub_2 &&
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SubIndices[3] == ARM::ssub_3) {
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if (Size >= 256)
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NewSubIdx = ARM::qsub_0;
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return true;
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}
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}
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} else if (NumRegs == 2) {
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if (SubIndices[0] == ARM::qsub_0) {
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// 2 Q registers -> 1 QQ register.
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if (Size >= 256 && SubIndices[1] == ARM::qsub_1) {
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if (Size == 512)
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NewSubIdx = ARM::qqsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::qsub_2) {
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// 2 Q registers -> 1 QQ register (2nd).
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if (Size == 512 && SubIndices[1] == ARM::qsub_3) {
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NewSubIdx = ARM::qqsub_1;
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return true;
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}
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} else if (SubIndices[0] == ARM::dsub_0) {
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// 2 D registers -> 1 Q register.
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if (Size >= 128 && SubIndices[1] == ARM::dsub_1) {
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if (Size >= 256)
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NewSubIdx = ARM::qsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::dsub_2) {
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// 2 D registers -> 1 Q register (2nd).
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if (Size >= 256 && SubIndices[1] == ARM::dsub_3) {
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NewSubIdx = ARM::qsub_1;
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return true;
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}
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} else if (SubIndices[0] == ARM::dsub_4) {
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// 2 D registers -> 1 Q register (3rd).
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if (Size == 512 && SubIndices[1] == ARM::dsub_5) {
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NewSubIdx = ARM::qsub_2;
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return true;
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}
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} else if (SubIndices[0] == ARM::dsub_6) {
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// 2 D registers -> 1 Q register (3rd).
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if (Size == 512 && SubIndices[1] == ARM::dsub_7) {
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NewSubIdx = ARM::qsub_3;
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return true;
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}
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} else if (SubIndices[0] == ARM::ssub_0) {
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// 2 S registers -> 1 D register.
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if (SubIndices[1] == ARM::ssub_1) {
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if (Size >= 128)
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NewSubIdx = ARM::dsub_0;
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return true;
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}
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} else if (SubIndices[0] == ARM::ssub_2) {
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// 2 S registers -> 1 D register (2nd).
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if (Size >= 128 && SubIndices[1] == ARM::ssub_3) {
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NewSubIdx = ARM::dsub_1;
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return true;
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}
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}
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}
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return false;
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}
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const TargetRegisterClass *
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ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
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return ARM::GPRRegisterClass;
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}
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unsigned
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ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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switch (RC->getID()) {
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default:
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return 0;
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case ARM::tGPRRegClassID:
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return TFI->hasFP(MF) ? 4 : 5;
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case ARM::GPRRegClassID: {
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unsigned FP = TFI->hasFP(MF) ? 1 : 0;
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return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
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}
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case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
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case ARM::DPRRegClassID:
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return 32 - 10;
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}
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}
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/// getAllocationOrder - Returns the register allocation order for a specified
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/// register class in the form of a pair of TargetRegisterClass iterators.
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std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
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ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
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unsigned HintType, unsigned HintReg,
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const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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// Alternative register allocation orders when favoring even / odd registers
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// of register pairs.
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// No FP, R9 is available.
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static const unsigned GPREven1[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
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ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
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ARM::R9, ARM::R11
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};
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static const unsigned GPROdd1[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
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ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
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ARM::R8, ARM::R10
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};
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// FP is R7, R9 is available.
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static const unsigned GPREven2[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R8, ARM::R10,
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ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
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ARM::R9, ARM::R11
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};
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static const unsigned GPROdd2[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R9, ARM::R11,
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ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
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ARM::R8, ARM::R10
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};
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// FP is R11, R9 is available.
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static const unsigned GPREven3[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
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ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
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ARM::R9
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};
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static const unsigned GPROdd3[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
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ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
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ARM::R8
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};
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// No FP, R9 is not available.
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static const unsigned GPREven4[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R10,
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ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
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ARM::R11
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};
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static const unsigned GPROdd4[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R11,
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ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
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ARM::R10
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};
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// FP is R7, R9 is not available.
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static const unsigned GPREven5[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R10,
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ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
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ARM::R11
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};
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static const unsigned GPROdd5[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R11,
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ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
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ARM::R10
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};
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// FP is R11, R9 is not available.
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static const unsigned GPREven6[] = {
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ARM::R0, ARM::R2, ARM::R4, ARM::R6,
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ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
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};
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static const unsigned GPROdd6[] = {
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ARM::R1, ARM::R3, ARM::R5, ARM::R7,
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ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
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};
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// We only support even/odd hints for GPR and rGPR.
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if (RC != ARM::GPRRegisterClass && RC != ARM::rGPRRegisterClass)
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return std::make_pair(RC->allocation_order_begin(MF),
|
|
RC->allocation_order_end(MF));
|
|
|
|
if (HintType == ARMRI::RegPairEven) {
|
|
if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
|
|
// It's no longer possible to fulfill this hint. Return the default
|
|
// allocation order.
|
|
return std::make_pair(RC->allocation_order_begin(MF),
|
|
RC->allocation_order_end(MF));
|
|
|
|
if (!TFI->hasFP(MF)) {
|
|
if (!STI.isR9Reserved())
|
|
return std::make_pair(GPREven1,
|
|
GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
|
|
else
|
|
return std::make_pair(GPREven4,
|
|
GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
|
|
} else if (FramePtr == ARM::R7) {
|
|
if (!STI.isR9Reserved())
|
|
return std::make_pair(GPREven2,
|
|
GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
|
|
else
|
|
return std::make_pair(GPREven5,
|
|
GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
|
|
} else { // FramePtr == ARM::R11
|
|
if (!STI.isR9Reserved())
|
|
return std::make_pair(GPREven3,
|
|
GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
|
|
else
|
|
return std::make_pair(GPREven6,
|
|
GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
|
|
}
|
|
} else if (HintType == ARMRI::RegPairOdd) {
|
|
if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
|
|
// It's no longer possible to fulfill this hint. Return the default
|
|
// allocation order.
|
|
return std::make_pair(RC->allocation_order_begin(MF),
|
|
RC->allocation_order_end(MF));
|
|
|
|
if (!TFI->hasFP(MF)) {
|
|
if (!STI.isR9Reserved())
|
|
return std::make_pair(GPROdd1,
|
|
GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
|
|
else
|
|
return std::make_pair(GPROdd4,
|
|
GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
|
|
} else if (FramePtr == ARM::R7) {
|
|
if (!STI.isR9Reserved())
|
|
return std::make_pair(GPROdd2,
|
|
GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
|
|
else
|
|
return std::make_pair(GPROdd5,
|
|
GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
|
|
} else { // FramePtr == ARM::R11
|
|
if (!STI.isR9Reserved())
|
|
return std::make_pair(GPROdd3,
|
|
GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
|
|
else
|
|
return std::make_pair(GPROdd6,
|
|
GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
|
|
}
|
|
}
|
|
return std::make_pair(RC->allocation_order_begin(MF),
|
|
RC->allocation_order_end(MF));
|
|
}
|
|
|
|
/// ResolveRegAllocHint - Resolves the specified register allocation hint
|
|
/// to a physical register. Returns the physical register if it is successful.
|
|
unsigned
|
|
ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
|
|
const MachineFunction &MF) const {
|
|
if (Reg == 0 || !isPhysicalRegister(Reg))
|
|
return 0;
|
|
if (Type == 0)
|
|
return Reg;
|
|
else if (Type == (unsigned)ARMRI::RegPairOdd)
|
|
// Odd register.
|
|
return getRegisterPairOdd(Reg, MF);
|
|
else if (Type == (unsigned)ARMRI::RegPairEven)
|
|
// Even register.
|
|
return getRegisterPairEven(Reg, MF);
|
|
return 0;
|
|
}
|
|
|
|
void
|
|
ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
|
|
MachineFunction &MF) const {
|
|
MachineRegisterInfo *MRI = &MF.getRegInfo();
|
|
std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
|
|
if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
|
|
Hint.first == (unsigned)ARMRI::RegPairEven) &&
|
|
TargetRegisterInfo::isVirtualRegister(Hint.second)) {
|
|
// If 'Reg' is one of the even / odd register pair and it's now changed
|
|
// (e.g. coalesced) into a different register. The other register of the
|
|
// pair allocation hint must be updated to reflect the relationship
|
|
// change.
|
|
unsigned OtherReg = Hint.second;
|
|
Hint = MRI->getRegAllocationHint(OtherReg);
|
|
if (Hint.second == Reg)
|
|
// Make sure the pair has not already divorced.
|
|
MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
|
|
}
|
|
}
|
|
|
|
bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
|
|
if (!EnableBasePointer)
|
|
return false;
|
|
|
|
if (needsStackRealignment(MF) && MFI->hasVarSizedObjects())
|
|
return true;
|
|
|
|
// Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
|
|
// negative range for ldr/str (255), and thumb1 is positive offsets only.
|
|
// It's going to be better to use the SP or Base Pointer instead. When there
|
|
// are variable sized objects, we can't reference off of the SP, so we
|
|
// reserve a Base Pointer.
|
|
if (AFI->isThumbFunction() && MFI->hasVarSizedObjects()) {
|
|
// Conservatively estimate whether the negative offset from the frame
|
|
// pointer will be sufficient to reach. If a function has a smallish
|
|
// frame, it's less likely to have lots of spills and callee saved
|
|
// space, so it's all more likely to be within range of the frame pointer.
|
|
// If it's wrong, the scavenger will still enable access to work, it just
|
|
// won't be optimal.
|
|
if (AFI->isThumb2Function() && MFI->getLocalFrameSize() < 128)
|
|
return false;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
// We can't realign the stack if:
|
|
// 1. Dynamic stack realignment is explicitly disabled,
|
|
// 2. This is a Thumb1 function (it's not useful, so we don't bother), or
|
|
// 3. There are VLAs in the function and the base pointer is disabled.
|
|
return (RealignStack && !AFI->isThumb1OnlyFunction() &&
|
|
(!MFI->hasVarSizedObjects() || EnableBasePointer));
|
|
}
|
|
|
|
bool ARMBaseRegisterInfo::
|
|
needsStackRealignment(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
const Function *F = MF.getFunction();
|
|
unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment();
|
|
bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) ||
|
|
F->hasFnAttr(Attribute::StackAlignment));
|
|
|
|
return requiresRealignment && canRealignStack(MF);
|
|
}
|
|
|
|
bool ARMBaseRegisterInfo::
|
|
cannotEliminateFrame(const MachineFunction &MF) const {
|
|
const MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
if (DisableFramePointerElim(MF) && MFI->adjustsStack())
|
|
return true;
|
|
return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken()
|
|
|| needsStackRealignment(MF);
|
|
}
|
|
|
|
unsigned ARMBaseRegisterInfo::getRARegister() const {
|
|
return ARM::LR;
|
|
}
|
|
|
|
unsigned
|
|
ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
|
|
if (TFI->hasFP(MF))
|
|
return FramePtr;
|
|
return ARM::SP;
|
|
}
|
|
|
|
unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
|
|
llvm_unreachable("What is the exception register");
|
|
return 0;
|
|
}
|
|
|
|
unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
|
|
llvm_unreachable("What is the exception handler register");
|
|
return 0;
|
|
}
|
|
|
|
int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
|
|
return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
|
|
}
|
|
|
|
unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
|
|
const MachineFunction &MF) const {
|
|
switch (Reg) {
|
|
default: break;
|
|
// Return 0 if either register of the pair is a special register.
|
|
// So no R12, etc.
|
|
case ARM::R1:
|
|
return ARM::R0;
|
|
case ARM::R3:
|
|
return ARM::R2;
|
|
case ARM::R5:
|
|
return ARM::R4;
|
|
case ARM::R7:
|
|
return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
|
|
? 0 : ARM::R6;
|
|
case ARM::R9:
|
|
return isReservedReg(MF, ARM::R9) ? 0 :ARM::R8;
|
|
case ARM::R11:
|
|
return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
|
|
|
|
case ARM::S1:
|
|
return ARM::S0;
|
|
case ARM::S3:
|
|
return ARM::S2;
|
|
case ARM::S5:
|
|
return ARM::S4;
|
|
case ARM::S7:
|
|
return ARM::S6;
|
|
case ARM::S9:
|
|
return ARM::S8;
|
|
case ARM::S11:
|
|
return ARM::S10;
|
|
case ARM::S13:
|
|
return ARM::S12;
|
|
case ARM::S15:
|
|
return ARM::S14;
|
|
case ARM::S17:
|
|
return ARM::S16;
|
|
case ARM::S19:
|
|
return ARM::S18;
|
|
case ARM::S21:
|
|
return ARM::S20;
|
|
case ARM::S23:
|
|
return ARM::S22;
|
|
case ARM::S25:
|
|
return ARM::S24;
|
|
case ARM::S27:
|
|
return ARM::S26;
|
|
case ARM::S29:
|
|
return ARM::S28;
|
|
case ARM::S31:
|
|
return ARM::S30;
|
|
|
|
case ARM::D1:
|
|
return ARM::D0;
|
|
case ARM::D3:
|
|
return ARM::D2;
|
|
case ARM::D5:
|
|
return ARM::D4;
|
|
case ARM::D7:
|
|
return ARM::D6;
|
|
case ARM::D9:
|
|
return ARM::D8;
|
|
case ARM::D11:
|
|
return ARM::D10;
|
|
case ARM::D13:
|
|
return ARM::D12;
|
|
case ARM::D15:
|
|
return ARM::D14;
|
|
case ARM::D17:
|
|
return ARM::D16;
|
|
case ARM::D19:
|
|
return ARM::D18;
|
|
case ARM::D21:
|
|
return ARM::D20;
|
|
case ARM::D23:
|
|
return ARM::D22;
|
|
case ARM::D25:
|
|
return ARM::D24;
|
|
case ARM::D27:
|
|
return ARM::D26;
|
|
case ARM::D29:
|
|
return ARM::D28;
|
|
case ARM::D31:
|
|
return ARM::D30;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
|
|
const MachineFunction &MF) const {
|
|
switch (Reg) {
|
|
default: break;
|
|
// Return 0 if either register of the pair is a special register.
|
|
// So no R12, etc.
|
|
case ARM::R0:
|
|
return ARM::R1;
|
|
case ARM::R2:
|
|
return ARM::R3;
|
|
case ARM::R4:
|
|
return ARM::R5;
|
|
case ARM::R6:
|
|
return (isReservedReg(MF, ARM::R7) || isReservedReg(MF, ARM::R6))
|
|
? 0 : ARM::R7;
|
|
case ARM::R8:
|
|
return isReservedReg(MF, ARM::R9) ? 0 :ARM::R9;
|
|
case ARM::R10:
|
|
return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
|
|
|
|
case ARM::S0:
|
|
return ARM::S1;
|
|
case ARM::S2:
|
|
return ARM::S3;
|
|
case ARM::S4:
|
|
return ARM::S5;
|
|
case ARM::S6:
|
|
return ARM::S7;
|
|
case ARM::S8:
|
|
return ARM::S9;
|
|
case ARM::S10:
|
|
return ARM::S11;
|
|
case ARM::S12:
|
|
return ARM::S13;
|
|
case ARM::S14:
|
|
return ARM::S15;
|
|
case ARM::S16:
|
|
return ARM::S17;
|
|
case ARM::S18:
|
|
return ARM::S19;
|
|
case ARM::S20:
|
|
return ARM::S21;
|
|
case ARM::S22:
|
|
return ARM::S23;
|
|
case ARM::S24:
|
|
return ARM::S25;
|
|
case ARM::S26:
|
|
return ARM::S27;
|
|
case ARM::S28:
|
|
return ARM::S29;
|
|
case ARM::S30:
|
|
return ARM::S31;
|
|
|
|
case ARM::D0:
|
|
return ARM::D1;
|
|
case ARM::D2:
|
|
return ARM::D3;
|
|
case ARM::D4:
|
|
return ARM::D5;
|
|
case ARM::D6:
|
|
return ARM::D7;
|
|
case ARM::D8:
|
|
return ARM::D9;
|
|
case ARM::D10:
|
|
return ARM::D11;
|
|
case ARM::D12:
|
|
return ARM::D13;
|
|
case ARM::D14:
|
|
return ARM::D15;
|
|
case ARM::D16:
|
|
return ARM::D17;
|
|
case ARM::D18:
|
|
return ARM::D19;
|
|
case ARM::D20:
|
|
return ARM::D21;
|
|
case ARM::D22:
|
|
return ARM::D23;
|
|
case ARM::D24:
|
|
return ARM::D25;
|
|
case ARM::D26:
|
|
return ARM::D27;
|
|
case ARM::D28:
|
|
return ARM::D29;
|
|
case ARM::D30:
|
|
return ARM::D31;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/// emitLoadConstPool - Emits a load from constpool to materialize the
|
|
/// specified immediate.
|
|
void ARMBaseRegisterInfo::
|
|
emitLoadConstPool(MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator &MBBI,
|
|
DebugLoc dl,
|
|
unsigned DestReg, unsigned SubIdx, int Val,
|
|
ARMCC::CondCodes Pred,
|
|
unsigned PredReg, unsigned MIFlags) const {
|
|
MachineFunction &MF = *MBB.getParent();
|
|
MachineConstantPool *ConstantPool = MF.getConstantPool();
|
|
const Constant *C =
|
|
ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
|
|
unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
|
|
|
|
BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
|
|
.addReg(DestReg, getDefRegState(true), SubIdx)
|
|
.addConstantPoolIndex(Idx)
|
|
.addImm(0).addImm(Pred).addReg(PredReg)
|
|
.setMIFlags(MIFlags);
|
|
}
|
|
|
|
bool ARMBaseRegisterInfo::
|
|
requiresRegisterScavenging(const MachineFunction &MF) const {
|
|
return true;
|
|
}
|
|
|
|
bool ARMBaseRegisterInfo::
|
|
requiresFrameIndexScavenging(const MachineFunction &MF) const {
|
|
return true;
|
|
}
|
|
|
|
bool ARMBaseRegisterInfo::
|
|
requiresVirtualBaseRegisters(const MachineFunction &MF) const {
|
|
return EnableLocalStackAlloc;
|
|
}
|
|
|
|
static void
|
|
emitSPUpdate(bool isARM,
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
|
|
DebugLoc dl, const ARMBaseInstrInfo &TII,
|
|
int NumBytes,
|
|
ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
|
|
if (isARM)
|
|
emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
|
|
Pred, PredReg, TII);
|
|
else
|
|
emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes,
|
|
Pred, PredReg, TII);
|
|
}
|
|
|
|
|
|
void ARMBaseRegisterInfo::
|
|
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
|
MachineBasicBlock::iterator I) const {
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
if (!TFI->hasReservedCallFrame(MF)) {
|
|
// If we have alloca, convert as follows:
|
|
// ADJCALLSTACKDOWN -> sub, sp, sp, amount
|
|
// ADJCALLSTACKUP -> add, sp, sp, amount
|
|
MachineInstr *Old = I;
|
|
DebugLoc dl = Old->getDebugLoc();
|
|
unsigned Amount = Old->getOperand(0).getImm();
|
|
if (Amount != 0) {
|
|
// We need to keep the stack aligned properly. To do this, we round the
|
|
// amount of space needed for the outgoing arguments up to the next
|
|
// alignment boundary.
|
|
unsigned Align = TFI->getStackAlignment();
|
|
Amount = (Amount+Align-1)/Align*Align;
|
|
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
assert(!AFI->isThumb1OnlyFunction() &&
|
|
"This eliminateCallFramePseudoInstr does not support Thumb1!");
|
|
bool isARM = !AFI->isThumbFunction();
|
|
|
|
// Replace the pseudo instruction with a new instruction...
|
|
unsigned Opc = Old->getOpcode();
|
|
int PIdx = Old->findFirstPredOperandIdx();
|
|
ARMCC::CondCodes Pred = (PIdx == -1)
|
|
? ARMCC::AL : (ARMCC::CondCodes)Old->getOperand(PIdx).getImm();
|
|
if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
|
|
// Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
|
|
unsigned PredReg = Old->getOperand(2).getReg();
|
|
emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg);
|
|
} else {
|
|
// Note: PredReg is operand 3 for ADJCALLSTACKUP.
|
|
unsigned PredReg = Old->getOperand(3).getReg();
|
|
assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
|
|
emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg);
|
|
}
|
|
}
|
|
}
|
|
MBB.erase(I);
|
|
}
|
|
|
|
int64_t ARMBaseRegisterInfo::
|
|
getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
|
|
const TargetInstrDesc &Desc = MI->getDesc();
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
|
int64_t InstrOffs = 0;;
|
|
int Scale = 1;
|
|
unsigned ImmIdx = 0;
|
|
switch (AddrMode) {
|
|
case ARMII::AddrModeT2_i8:
|
|
case ARMII::AddrModeT2_i12:
|
|
case ARMII::AddrMode_i12:
|
|
InstrOffs = MI->getOperand(Idx+1).getImm();
|
|
Scale = 1;
|
|
break;
|
|
case ARMII::AddrMode5: {
|
|
// VFP address mode.
|
|
const MachineOperand &OffOp = MI->getOperand(Idx+1);
|
|
InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
|
|
if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
|
|
InstrOffs = -InstrOffs;
|
|
Scale = 4;
|
|
break;
|
|
}
|
|
case ARMII::AddrMode2: {
|
|
ImmIdx = Idx+2;
|
|
InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
|
|
if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
InstrOffs = -InstrOffs;
|
|
break;
|
|
}
|
|
case ARMII::AddrMode3: {
|
|
ImmIdx = Idx+2;
|
|
InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
|
|
if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
|
|
InstrOffs = -InstrOffs;
|
|
break;
|
|
}
|
|
case ARMII::AddrModeT1_s: {
|
|
ImmIdx = Idx+1;
|
|
InstrOffs = MI->getOperand(ImmIdx).getImm();
|
|
Scale = 4;
|
|
break;
|
|
}
|
|
default:
|
|
llvm_unreachable("Unsupported addressing mode!");
|
|
break;
|
|
}
|
|
|
|
return InstrOffs * Scale;
|
|
}
|
|
|
|
/// needsFrameBaseReg - Returns true if the instruction's frame index
|
|
/// reference would be better served by a base register other than FP
|
|
/// or SP. Used by LocalStackFrameAllocation to determine which frame index
|
|
/// references it should create new base registers for.
|
|
bool ARMBaseRegisterInfo::
|
|
needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
|
|
for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
|
|
assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
|
|
}
|
|
|
|
// It's the load/store FI references that cause issues, as it can be difficult
|
|
// to materialize the offset if it won't fit in the literal field. Estimate
|
|
// based on the size of the local frame and some conservative assumptions
|
|
// about the rest of the stack frame (note, this is pre-regalloc, so
|
|
// we don't know everything for certain yet) whether this offset is likely
|
|
// to be out of range of the immediate. Return true if so.
|
|
|
|
// We only generate virtual base registers for loads and stores, so
|
|
// return false for everything else.
|
|
unsigned Opc = MI->getOpcode();
|
|
switch (Opc) {
|
|
case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
|
|
case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
|
|
case ARM::t2LDRi12: case ARM::t2LDRi8:
|
|
case ARM::t2STRi12: case ARM::t2STRi8:
|
|
case ARM::VLDRS: case ARM::VLDRD:
|
|
case ARM::VSTRS: case ARM::VSTRD:
|
|
case ARM::tSTRspi: case ARM::tLDRspi:
|
|
if (ForceAllBaseRegAlloc)
|
|
return true;
|
|
break;
|
|
default:
|
|
return false;
|
|
}
|
|
|
|
// Without a virtual base register, if the function has variable sized
|
|
// objects, all fixed-size local references will be via the frame pointer,
|
|
// Approximate the offset and see if it's legal for the instruction.
|
|
// Note that the incoming offset is based on the SP value at function entry,
|
|
// so it'll be negative.
|
|
MachineFunction &MF = *MI->getParent()->getParent();
|
|
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
|
|
// Estimate an offset from the frame pointer.
|
|
// Conservatively assume all callee-saved registers get pushed. R4-R6
|
|
// will be earlier than the FP, so we ignore those.
|
|
// R7, LR
|
|
int64_t FPOffset = Offset - 8;
|
|
// ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
|
|
if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
|
|
FPOffset -= 80;
|
|
// Estimate an offset from the stack pointer.
|
|
// The incoming offset is relating to the SP at the start of the function,
|
|
// but when we access the local it'll be relative to the SP after local
|
|
// allocation, so adjust our SP-relative offset by that allocation size.
|
|
Offset = -Offset;
|
|
Offset += MFI->getLocalFrameSize();
|
|
// Assume that we'll have at least some spill slots allocated.
|
|
// FIXME: This is a total SWAG number. We should run some statistics
|
|
// and pick a real one.
|
|
Offset += 128; // 128 bytes of spill slots
|
|
|
|
// If there is a frame pointer, try using it.
|
|
// The FP is only available if there is no dynamic realignment. We
|
|
// don't know for sure yet whether we'll need that, so we guess based
|
|
// on whether there are any local variables that would trigger it.
|
|
unsigned StackAlign = TFI->getStackAlignment();
|
|
if (TFI->hasFP(MF) &&
|
|
!((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
|
|
if (isFrameOffsetLegal(MI, FPOffset))
|
|
return false;
|
|
}
|
|
// If we can reference via the stack pointer, try that.
|
|
// FIXME: This (and the code that resolves the references) can be improved
|
|
// to only disallow SP relative references in the live range of
|
|
// the VLA(s). In practice, it's unclear how much difference that
|
|
// would make, but it may be worth doing.
|
|
if (!MFI->hasVarSizedObjects() && isFrameOffsetLegal(MI, Offset))
|
|
return false;
|
|
|
|
// The offset likely isn't legal, we want to allocate a virtual base register.
|
|
return true;
|
|
}
|
|
|
|
/// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
|
|
/// be a pointer to FrameIdx at the beginning of the basic block.
|
|
void ARMBaseRegisterInfo::
|
|
materializeFrameBaseRegister(MachineBasicBlock *MBB,
|
|
unsigned BaseReg, int FrameIdx,
|
|
int64_t Offset) const {
|
|
ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
|
|
unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
|
|
(AFI->isThumb1OnlyFunction() ? ARM::tADDrSPi : ARM::t2ADDri);
|
|
|
|
MachineBasicBlock::iterator Ins = MBB->begin();
|
|
DebugLoc DL; // Defaults to "unknown"
|
|
if (Ins != MBB->end())
|
|
DL = Ins->getDebugLoc();
|
|
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(*MBB, Ins, DL, TII.get(ADDriOpc), BaseReg)
|
|
.addFrameIndex(FrameIdx).addImm(Offset);
|
|
|
|
if (!AFI->isThumb1OnlyFunction())
|
|
AddDefaultCC(AddDefaultPred(MIB));
|
|
}
|
|
|
|
void
|
|
ARMBaseRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
|
|
unsigned BaseReg, int64_t Offset) const {
|
|
MachineInstr &MI = *I;
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
MachineFunction &MF = *MBB.getParent();
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
int Off = Offset; // ARM doesn't need the general 64-bit offsets
|
|
unsigned i = 0;
|
|
|
|
assert(!AFI->isThumb1OnlyFunction() &&
|
|
"This resolveFrameIndex does not support Thumb1!");
|
|
|
|
while (!MI.getOperand(i).isFI()) {
|
|
++i;
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
}
|
|
bool Done = false;
|
|
if (!AFI->isThumbFunction())
|
|
Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
|
|
else {
|
|
assert(AFI->isThumb2Function());
|
|
Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
|
|
}
|
|
assert (Done && "Unable to resolve frame index!");
|
|
}
|
|
|
|
bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
|
|
int64_t Offset) const {
|
|
const TargetInstrDesc &Desc = MI->getDesc();
|
|
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
|
|
unsigned i = 0;
|
|
|
|
while (!MI->getOperand(i).isFI()) {
|
|
++i;
|
|
assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
|
|
}
|
|
|
|
// AddrMode4 and AddrMode6 cannot handle any offset.
|
|
if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
|
|
return Offset == 0;
|
|
|
|
unsigned NumBits = 0;
|
|
unsigned Scale = 1;
|
|
bool isSigned = true;
|
|
switch (AddrMode) {
|
|
case ARMII::AddrModeT2_i8:
|
|
case ARMII::AddrModeT2_i12:
|
|
// i8 supports only negative, and i12 supports only positive, so
|
|
// based on Offset sign, consider the appropriate instruction
|
|
Scale = 1;
|
|
if (Offset < 0) {
|
|
NumBits = 8;
|
|
Offset = -Offset;
|
|
} else {
|
|
NumBits = 12;
|
|
}
|
|
break;
|
|
case ARMII::AddrMode5:
|
|
// VFP address mode.
|
|
NumBits = 8;
|
|
Scale = 4;
|
|
break;
|
|
case ARMII::AddrMode_i12:
|
|
case ARMII::AddrMode2:
|
|
NumBits = 12;
|
|
break;
|
|
case ARMII::AddrMode3:
|
|
NumBits = 8;
|
|
break;
|
|
case ARMII::AddrModeT1_s:
|
|
NumBits = 5;
|
|
Scale = 4;
|
|
isSigned = false;
|
|
break;
|
|
default:
|
|
llvm_unreachable("Unsupported addressing mode!");
|
|
break;
|
|
}
|
|
|
|
Offset += getFrameIndexInstrOffset(MI, i);
|
|
// Make sure the offset is encodable for instructions that scale the
|
|
// immediate.
|
|
if ((Offset & (Scale-1)) != 0)
|
|
return false;
|
|
|
|
if (isSigned && Offset < 0)
|
|
Offset = -Offset;
|
|
|
|
unsigned Mask = (1 << NumBits) - 1;
|
|
if ((unsigned)Offset <= Mask * Scale)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
void
|
|
ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
|
|
int SPAdj, RegScavenger *RS) const {
|
|
unsigned i = 0;
|
|
MachineInstr &MI = *II;
|
|
MachineBasicBlock &MBB = *MI.getParent();
|
|
MachineFunction &MF = *MBB.getParent();
|
|
const ARMFrameLowering *TFI =
|
|
static_cast<const ARMFrameLowering*>(MF.getTarget().getFrameLowering());
|
|
ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
|
|
assert(!AFI->isThumb1OnlyFunction() &&
|
|
"This eliminateFrameIndex does not support Thumb1!");
|
|
|
|
while (!MI.getOperand(i).isFI()) {
|
|
++i;
|
|
assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
|
|
}
|
|
|
|
int FrameIndex = MI.getOperand(i).getIndex();
|
|
unsigned FrameReg;
|
|
|
|
int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
|
|
|
|
// Special handling of dbg_value instructions.
|
|
if (MI.isDebugValue()) {
|
|
MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
|
|
MI.getOperand(i+1).ChangeToImmediate(Offset);
|
|
return;
|
|
}
|
|
|
|
// Modify MI as necessary to handle as much of 'Offset' as possible
|
|
bool Done = false;
|
|
if (!AFI->isThumbFunction())
|
|
Done = rewriteARMFrameIndex(MI, i, FrameReg, Offset, TII);
|
|
else {
|
|
assert(AFI->isThumb2Function());
|
|
Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
|
|
}
|
|
if (Done)
|
|
return;
|
|
|
|
// If we get here, the immediate doesn't fit into the instruction. We folded
|
|
// as much as possible above, handle the rest, providing a register that is
|
|
// SP+LargeImm.
|
|
assert((Offset ||
|
|
(MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
|
|
(MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
|
|
"This code isn't needed if offset already handled!");
|
|
|
|
unsigned ScratchReg = 0;
|
|
int PIdx = MI.findFirstPredOperandIdx();
|
|
ARMCC::CondCodes Pred = (PIdx == -1)
|
|
? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
|
|
unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
|
|
if (Offset == 0)
|
|
// Must be addrmode4/6.
|
|
MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
|
|
else {
|
|
ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
|
|
if (!AFI->isThumbFunction())
|
|
emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
|
|
Offset, Pred, PredReg, TII);
|
|
else {
|
|
assert(AFI->isThumb2Function());
|
|
emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
|
|
Offset, Pred, PredReg, TII);
|
|
}
|
|
// Update the original instruction to use the scratch register.
|
|
MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
|
|
if (MI.getOpcode() == ARM::t2ADDrSPi)
|
|
MI.setDesc(TII.get(ARM::t2ADDri));
|
|
else if (MI.getOpcode() == ARM::t2SUBrSPi)
|
|
MI.setDesc(TII.get(ARM::t2SUBri));
|
|
}
|
|
}
|
|
|
|
#include "ARMGenRegisterInfo.inc"
|