mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-05 13:29:22 +00:00
5bafff36c7
This is still a work in progress but most of the NEON instruction set is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
303 lines
11 KiB
LLVM
303 lines
11 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vshl\\.s8} %t | count 2
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; RUN: grep {vshl\\.s16} %t | count 2
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; RUN: grep {vshl\\.s32} %t | count 2
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; RUN: grep {vshl\\.s64} %t | count 2
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; RUN: grep {vshl\\.u8} %t | count 2
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; RUN: grep {vshl\\.u16} %t | count 2
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; RUN: grep {vshl\\.u32} %t | count 2
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; RUN: grep {vshl\\.u64} %t | count 2
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; RUN: grep {vshl\\.i8} %t | count 2
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; RUN: grep {vshl\\.i16} %t | count 2
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; RUN: grep {vshl\\.i32} %t | count 2
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; RUN: grep {vshl\\.i64} %t | count 2
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; RUN: grep {vshr\\.s8} %t | count 2
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; RUN: grep {vshr\\.s16} %t | count 2
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; RUN: grep {vshr\\.s32} %t | count 2
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; RUN: grep {vshr\\.s64} %t | count 2
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; RUN: grep {vshr\\.u8} %t | count 2
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; RUN: grep {vshr\\.u16} %t | count 2
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; RUN: grep {vshr\\.u32} %t | count 2
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; RUN: grep {vshr\\.u64} %t | count 2
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define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
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ret <1 x i64> %tmp3
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}
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define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
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%tmp1 = load <1 x i64>* %A
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%tmp2 = load <1 x i64>* %B
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%tmp3 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)
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ret <1 x i64> %tmp3
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}
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define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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; For left shifts by immediates, the signedness is irrelevant.
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; Test a mix of both signed and unsigned intrinsics.
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define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
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%tmp1 = load <1 x i64>* %A
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%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
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ret <1 x i64> %tmp2
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}
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define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
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ret <2 x i64> %tmp2
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}
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; Right shift by immediate:
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define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
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%tmp1 = load <1 x i64>* %A
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%tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
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ret <1 x i64> %tmp2
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}
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define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
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%tmp1 = load <8 x i8>* %A
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%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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ret <8 x i8> %tmp2
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}
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define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
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%tmp1 = load <4 x i16>* %A
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%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
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ret <4 x i16> %tmp2
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}
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define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
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ret <2 x i32> %tmp2
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}
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define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
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%tmp1 = load <1 x i64>* %A
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%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
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ret <1 x i64> %tmp2
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}
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define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
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ret <2 x i64> %tmp2
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}
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define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
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%tmp1 = load <16 x i8>* %A
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%tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
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ret <16 x i8> %tmp2
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}
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define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
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%tmp1 = load <8 x i16>* %A
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%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
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ret <8 x i16> %tmp2
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}
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define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
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ret <4 x i32> %tmp2
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}
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define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind {
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%tmp1 = load <2 x i64>* %A
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%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
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ret <2 x i64> %tmp2
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}
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declare <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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declare <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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