Venkatraman Govindaraju 5d02c84191 [Sparc] Add initial implementation of MC Code emitter for sparc. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198533 91177308-0d34-0410-b5e6-96231b3b80d8		2014-01-05 02:13:48 +00:00
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AArch64	[AArch64][NEON] Added SXTL and SXTL2 instruction aliases	2014-01-03 19:20:31 +00:00
ARM	[arm] Add softvfp to supported FPU names.	2014-01-02 15:50:02 +00:00
AsmParser	Mark the 64-bit x86 push/pop instructions as In64BitMode. Mark the corresponding 32-bit versions with the same encodings Not64BitMode. Remove hack from tablegen disassembler table emitter. Fix bad test.	2014-01-05 01:35:51 +00:00
COFF	Add the .secidx test I've forgotten to svn add in 197826	2013-12-20 19:06:50 +00:00
Disassembler	Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.	2014-01-01 15:29:32 +00:00
ELF
MachO
Markup
Mips	Support for microMIPS load effective address.	2013-12-25 10:14:07 +00:00
PowerPC
Sparc	[Sparc] Add initial implementation of MC Code emitter for sparc.	2014-01-05 02:13:48 +00:00
SystemZ	[SystemZ] Add MC support for interlocked-access 1 instructions	2013-12-24 15:14:05 +00:00
X86