Tim Northover 5d8c2e460c DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswap ... We want to convert code like (or (srl N, 8), (shl N, 8)) into (srl (bswap N), const), but this is only valid if the bits above 16 on the source pattern are 0, the checks we were doing on this were slightly wrong before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189348 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-27 13:46:45 +00:00
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AArch64	A minor change for an obvous problem caused by r188451:	2013-08-21 17:47:53 +00:00
ARM	ARM: add natural patterns for vaddhl and vsubhl.	2013-08-27 10:31:36 +00:00
CPP	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
Generic	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
Hexagon	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Inputs	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Mips	[mips][msa] Added tests for and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v when non-byte vectors are used.	2013-08-27 10:16:17 +00:00
MSP430	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00
NVPTX	[NVPTX] Re-enable assembly printing support for inline assembly	2013-08-24 01:17:23 +00:00
PowerPC	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
R600	R600/SI: Enable local-memory-two-objects lit test	2013-08-27 10:28:26 +00:00
SPARC	[Sparc] Add long double (f128) instructions to sparc backend.	2013-08-25 18:30:06 +00:00
SystemZ	[SystemZ] Extend memcpy and memset support to all constant lengths	2013-08-27 09:54:29 +00:00
Thumb	Debug Info: add an identifier field to DICompositeType.	2013-08-26 22:39:55 +00:00
Thumb2	ARM: make sure ARM-mode pseudo-inst requires IsARM	2013-08-23 10:16:39 +00:00
X86	DAGCombiner: make sure or/shl/srl really has zero high bits before forming bswap	2013-08-27 13:46:45 +00:00
XCore	[tests] Cleanup initialization of test suffixes.	2013-08-16 00:37:11 +00:00