Chad Rosier 5e3288f85b [FastISel][AArch64] Also allow folding of sign-/zero-extend and logical ... shift-right for booleans (i1). Logical shift-right immediate with sign-/zero-extensions also works for boolean values. Update the assert and the test cases to reflect that fact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222270 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-18 22:38:42 +00:00
..
AsmParser
Disassembler
InstPrinter
MCTargetDesc
TargetInfo
Utils
AArch64.h
AArch64.td
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AddressTypePromotion.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp
AArch64BranchRelaxation.cpp
AArch64CallingConvention.td
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp
AArch64FastISel.cpp	[FastISel][AArch64] Also allow folding of sign-/zero-extend and logical	2014-11-18 22:38:42 +00:00
AArch64FrameLowering.cpp
AArch64FrameLowering.h
AArch64InstrAtomics.td
AArch64InstrFormats.td
AArch64InstrInfo.cpp
AArch64InstrInfo.h
AArch64InstrInfo.td
AArch64ISelDAGToDAG.cpp
AArch64ISelLowering.cpp
AArch64ISelLowering.h
AArch64LoadStoreOptimizer.cpp
AArch64MachineCombinerPattern.h
AArch64MachineFunctionInfo.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RegisterInfo.cpp
AArch64RegisterInfo.h
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp
AArch64Subtarget.h
AArch64TargetMachine.cpp
AArch64TargetMachine.h
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp
CMakeLists.txt
LLVMBuild.txt
Makefile