llvm-6502/lib/Target/CellSPU
Dmitri Gribenko c5252da873 Fix Doxygen issues:
* wrap code blocks in \code ... \endcode;
* refer to parameter names in paragraphs correctly (\arg is not what most
  people want -- it starts a new paragraph);
* use \param instead of \arg to document parameters in order to be consistent
  with the rest of the codebase.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163902 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-14 14:57:36 +00:00
..
MCTargetDesc Remove some unnecessary forward declarations. 2012-03-22 06:52:14 +00:00
TargetInfo LLVMBuild: Remove trailing newline, which irked me. 2011-12-12 19:48:00 +00:00
CellSDKIntrinsics.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
CMakeLists.txt llvm/lib: [CMake] Add explicit dependency to intrinsics_gen. 2012-06-24 13:32:01 +00:00
LLVMBuild.txt LLVMBuild: Introduce a common section which currently has a list of the 2011-12-12 22:45:54 +00:00
Makefile
README.txt Update the documentation of CellSPU, in case it gets removed in 3.1. 2012-04-29 20:00:55 +00:00
SPU64InstrInfo.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPU128InstrInfo.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPU.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPU.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPUAsmPrinter.cpp Fix integer undefined behavior due to signed left shift overflow in LLVM. 2012-08-24 23:29:28 +00:00
SPUCallingConv.td Remove unused CCIfSubtarget. 2012-04-17 11:29:05 +00:00
SPUFrameLowering.cpp Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
SPUFrameLowering.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPUHazardRecognizers.cpp Round 2 of dead private variable removal. 2012-06-06 19:47:08 +00:00
SPUHazardRecognizers.h Round 2 of dead private variable removal. 2012-06-06 19:47:08 +00:00
SPUInstrBuilder.h Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPUInstrFormats.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPUInstrInfo.cpp Remove tabs. 2012-07-19 00:06:06 +00:00
SPUInstrInfo.h Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00
SPUInstrInfo.td Remove variable_ops from call instructions in most targets. 2012-07-13 20:44:29 +00:00
SPUISelDAGToDAG.cpp Fix Doxygen issues: 2012-09-14 14:57:36 +00:00
SPUISelLowering.cpp Remove tabs. 2012-07-19 00:11:40 +00:00
SPUISelLowering.h Round 2 of dead private variable removal. 2012-06-06 19:47:08 +00:00
SPUMachineFunction.cpp Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPUMachineFunction.h Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SPUMathInstr.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPUNodes.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPUNopFiller.cpp Revert r158679 - use case is unclear (and it increases the memory footprint). 2012-06-22 20:27:13 +00:00
SPUOperands.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPURegisterInfo.cpp Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
SPURegisterInfo.h Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 2012-05-07 22:10:26 +00:00
SPURegisterInfo.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPURegisterNames.h
SPUSchedule.td Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 2012-02-18 12:03:15 +00:00
SPUSelectionDAGInfo.cpp
SPUSelectionDAGInfo.h
SPUSubtarget.cpp Prune some includes 2012-03-27 07:54:11 +00:00
SPUSubtarget.h
SPUTargetMachine.cpp Add all codegen passes to the PassManager via TargetPassConfig. 2012-07-02 19:48:31 +00:00
SPUTargetMachine.h Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 2012-03-17 18:46:09 +00:00

//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//

This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:

- Scott Michel (head bottle washer and much of the non-floating point
  instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)
- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)

Some minor fixes added by Kalle Raiskila.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE.

---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:

If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:

        ./configure <your_configure_flags_here> \
           --enable-targets=x86,x86_64,powerpc,spu

---------------------------------------------------------------------------

TODO:
* In commit r142152 vector legalization was set to element promotion per
  default. This breaks half vectors (e.g. v2i32) badly as they get element
  promoted to much slower types (v2i64).

* Many CellSPU specific codegen tests only grep & count the number of 
  instructions, not checking their place with FileCheck. There have also
  been some commits that change the CellSPU checks, some of which might
  have not been thoroughly scrutinized w.r.t. to the changes they cause in SPU
  assembly. (especially since about the time of r142152)  

* Some of the i64 math have huge tablegen rules, which sometime cause
  tablegen to run out of memory. See e.g. bug 8850. i64 arithmetics 
  should probably be done with libraries.

* Create a machine pass for performing dual-pipeline scheduling specifically
  for CellSPU, and insert branch prediction instructions as needed.

* i32 instructions:

  * i32 division (work-in-progress)

* i64 support (see i64operations.c test harness):

  * shifts and comparison operators: done
  * sign and zero extension: done
  * addition: done
  * subtraction: needed
  * multiplication: done

* i128 support:

  * zero extension, any extension: done
  * sign extension: done
  * arithmetic operators (add, sub, mul, div): needed
  * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed

    * or: done

* f64 support

  * Comparison operators:
    SETOEQ              unimplemented
    SETOGT              unimplemented
    SETOGE              unimplemented
    SETOLT              unimplemented
    SETOLE              unimplemented
    SETONE              unimplemented
    SETO                done (lowered)
    SETUO               done (lowered)
    SETUEQ              unimplemented
    SETUGT              unimplemented
    SETUGE              unimplemented
    SETULT              unimplemented
    SETULE              unimplemented
    SETUNE              unimplemented

* LLVM vector suport

  * VSETCC needs to be implemented. It's pretty straightforward to code, but
    needs implementation.

* Intrinsics

  * spu.h instrinsics added but not tested. Need to have an operational
    llvm-spu-gcc in order to write a unit test harness.

===-------------------------------------------------------------------------===