Vikram S. Adve 5f2180c533 (1) Added special register class containing (for now) %fsr. ... Fixed spilling of %fcc[0-3] which are part of %fsr. (2) Moved some machine-independent reg-class code to class TargetRegInfo from SparcReg{Class,}Info. (3) Renamed MachienOperand::opIsDef to MachineOperand::opIsDefOnly() and related functions and flags. Fixed several bugs where only "isDef" was being checked, not "isDefAndUse". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6341 91177308-0d34-0410-b5e6-96231b3b80d8		2003-05-27 00:05:23 +00:00
..
CBackend	Add support for setjmp/longjmp primitives	2003-05-17 22:26:33 +00:00
SparcV9	(1) Added special register class containing (for now) %fsr.	2003-05-27 00:05:23 +00:00
X86	Renamed opIsDef to opIsDefOnly.	2003-05-27 00:03:17 +00:00
Makefile
MRegisterInfo.cpp
TargetData.cpp	* Fix divide by zero error with empty structs	2003-05-21 18:08:44 +00:00
TargetInstrInfo.cpp	Rename MachineInstrInfo -> TargetInstrInfo	2003-01-14 22:00:31 +00:00
TargetMachine.cpp	The promotion rules are the same for all targets, they are set by the C standard.	2003-04-26 19:47:36 +00:00
TargetSchedInfo.cpp