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* vreg <-> vreg joining now works, enable it unconditionally when joining is enabled (which is the default). * Fix a serious pessimization of spill code where we were saying that a spilled DEF operand was live into the subsequent instruction. This allows for substantially better code when spilling starts to happen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14993 91177308-0d34-0410-b5e6-96231b3b80d8 |
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.. | ||
InstrSched | ||
ModuloScheduling | ||
SelectionDAG | ||
IntrinsicLowering.cpp | ||
LiveIntervalAnalysis.cpp | ||
LiveIntervalAnalysis.h | ||
LiveVariables.cpp | ||
MachineBasicBlock.cpp | ||
MachineCodeEmitter.cpp | ||
MachineCodeForInstruction.cpp | ||
MachineFunction.cpp | ||
MachineInstr.cpp | ||
MachineInstrAnnot.cpp | ||
Makefile | ||
Passes.cpp | ||
PHIElimination.cpp | ||
PhysRegTracker.h | ||
PrologEpilogInserter.cpp | ||
RegAllocLinearScan.cpp | ||
RegAllocLocal.cpp | ||
RegAllocSimple.cpp | ||
TwoAddressInstructionPass.cpp | ||
UnreachableBlockElim.cpp | ||
VirtRegMap.cpp | ||
VirtRegMap.h |