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https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
98 lines
2.2 KiB
LLVM
98 lines
2.2 KiB
LLVM
; Verify that i32 argument/return values are extended to i64
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; RUN: llc < %s | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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@si = common global i32 0, align 4
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@ui = common global i32 0, align 4
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declare void @arg_si(i32 signext)
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declare void @arg_ui(i32 zeroext)
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declare signext i32 @ret_si()
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declare zeroext i32 @ret_ui()
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define void @pass_arg_si() nounwind {
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entry:
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%0 = load i32, i32* @si, align 4
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tail call void @arg_si(i32 signext %0) nounwind
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ret void
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}
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; CHECK: @pass_arg_si
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; CHECK: lwa 3,
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; CHECK: bl arg_si
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define void @pass_arg_ui() nounwind {
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entry:
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%0 = load i32, i32* @ui, align 4
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tail call void @arg_ui(i32 zeroext %0) nounwind
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ret void
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}
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; CHECK: @pass_arg_ui
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; CHECK: lwz 3,
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; CHECK: bl arg_ui
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define i64 @use_arg_si(i32 signext %x) nounwind readnone {
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entry:
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%conv = sext i32 %x to i64
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ret i64 %conv
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}
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; CHECK: @use_arg_si
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; CHECK: %entry
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; CHECK-NEXT: blr
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define i64 @use_arg_ui(i32 zeroext %x) nounwind readnone {
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entry:
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%conv = zext i32 %x to i64
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ret i64 %conv
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}
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; CHECK: @use_arg_ui
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; CHECK: %entry
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; CHECK-NEXT: blr
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define signext i32 @pass_ret_si() nounwind readonly {
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entry:
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%0 = load i32, i32* @si, align 4
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ret i32 %0
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}
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; CHECK: @pass_ret_si
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; CHECK: lwa 3,
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; CHECK: blr
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define zeroext i32 @pass_ret_ui() nounwind readonly {
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entry:
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%0 = load i32, i32* @ui, align 4
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ret i32 %0
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}
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; CHECK: @pass_ret_ui
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; CHECK: lwz 3,
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; CHECK: blr
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define i64 @use_ret_si() nounwind {
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entry:
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%call = tail call signext i32 @ret_si() nounwind
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%conv = sext i32 %call to i64
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ret i64 %conv
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}
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; CHECK: @use_ret_si
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; CHECK: bl ret_si
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; This is to verify the return register (3) set up by the ret_si
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; call is passed on unmodified as return value of use_ret_si.
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; CHECK-NOT: 3
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; CHECK: blr
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define i64 @use_ret_ui() nounwind {
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entry:
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%call = tail call zeroext i32 @ret_ui() nounwind
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%conv = zext i32 %call to i64
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ret i64 %conv
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}
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; CHECK: @use_ret_ui
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; CHECK: bl ret_ui
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; This is to verify the return register (3) set up by the ret_ui
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; call is passed on unmodified as return value of use_ret_ui.
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; CHECK-NOT: 3
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; CHECK: blr
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