Colin LeMahieu 60b4c7fc30 [Hexagon] Adding functionality for duplexing. Duplexing is a way to compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements. ...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239095 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-04 21:16:16 +00:00

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AArch64

[GlobalMerge] Take into account minsize on Global users' parents.

2015-06-04 20:39:23 +00:00

ARM

ARM: Thumb2 LDRD/STRD supports independent input/output regs

2015-06-03 16:30:24 +00:00

BPF

[bpf] add big- and host- endian support

2015-06-04 19:15:05 +00:00

CPP

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Generic

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Hexagon

[Hexagon] Adding functionality for duplexing. Duplexing is a way to compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements.

2015-06-04 21:16:16 +00:00

Inputs

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Mips

[mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.

2015-06-02 20:32:50 +00:00

MIR

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MSP430

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NVPTX

Revert r239082

2015-06-04 21:07:08 +00:00

PowerPC

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R600

R600/SI: Reimplement isLegalAddressingMode

2015-06-04 16:17:42 +00:00

SPARC

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SystemZ

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Thumb

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Thumb2

ARM: Thumb2 LDRD/STRD supports independent input/output regs

2015-06-03 16:30:24 +00:00

WinEH

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X86

[DAGCombiner] Fix wrong folding of a build_vector into a blend with zero.

2015-06-04 19:15:01 +00:00

XCore

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