mirror of
https://github.com/c64scene-ar/llvm-6502.git
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87d1836793
This patch improves support for sign extension of the lower lanes of vectors of integers by making use of the SSE41 pmovsx* sign extension instructions where possible, and optimizing the sign extension by shifts on pre-SSE41 targets (avoiding the use of i64 arithmetic shifts which require scalarization). It converts SIGN_EXTEND nodes to SIGN_EXTEND_VECTOR_INREG where necessary, that more closely matches the pmovsx* instruction than the default approach of using SIGN_EXTEND_INREG which splits the operation (into an ANY_EXTEND lowered to a shuffle followed by shifts) making instruction matching difficult during lowering. Necessary support for SIGN_EXTEND_VECTOR_INREG has been added to the DAGCombiner. Differential Revision: http://reviews.llvm.org/D9848 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237885 91177308-0d34-0410-b5e6-96231b3b80d8
139 lines
2.6 KiB
LLVM
139 lines
2.6 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7-avx | FileCheck %s
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define <4 x i3> @test1(<4 x i3>* %in) nounwind {
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%ret = load <4 x i3>, <4 x i3>* %in, align 1
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ret <4 x i3> %ret
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}
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; CHECK-LABEL: test1
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; CHECK: movzwl
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; CHECK: shrl $3
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; CHECK: andl $7
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; CHECK: andl $7
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; CHECK: vmovd
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; CHECK: pinsrd $1
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; CHECK: shrl $6
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; CHECK: andl $7
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; CHECK: pinsrd $2
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; CHECK: shrl $9
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; CHECK: andl $7
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; CHECK: pinsrd $3
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; CHECK: ret
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define <4 x i1> @test2(<4 x i1>* %in) nounwind {
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%ret = load <4 x i1>, <4 x i1>* %in, align 1
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ret <4 x i1> %ret
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}
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; CHECK-LABEL: test2
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; CHECK: movzbl
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; CHECK: shrl
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; CHECK: andl $1
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; CHECK: andl $1
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; CHECK: vmovd
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; CHECK: pinsrd $1
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; CHECK: shrl $2
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; CHECK: andl $1
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; CHECK: pinsrd $2
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; CHECK: shrl $3
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; CHECK: andl $1
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; CHECK: pinsrd $3
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; CHECK: ret
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define <4 x i64> @test3(<4 x i1>* %in) nounwind {
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%wide.load35 = load <4 x i1>, <4 x i1>* %in, align 1
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%sext = sext <4 x i1> %wide.load35 to <4 x i64>
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ret <4 x i64> %sext
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}
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; CHECK-LABEL: test3
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; CHECK: movzbl
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; CHECK: movq
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; CHECK: shlq
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; CHECK: sarq
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; CHECK: movq
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; CHECK: shlq
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; CHECK: sarq
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; CHECK: vmovd
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; CHECK: vpinsrd
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; CHECK: movq
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; CHECK: shlq
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; CHECK: sarq
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; CHECK: vpinsrd
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; CHECK: shlq
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; CHECK: sarq
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; CHECK: vpinsrd
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; CHECK: vpmovsxdq
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; CHECK: vmovd
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; CHECK: vpinsrd
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; CHECK: vpmovsxdq
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; CHECK: vinsertf128
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; CHECK: ret
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define <16 x i4> @test4(<16 x i4>* %in) nounwind {
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%ret = load <16 x i4>, <16 x i4>* %in, align 1
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ret <16 x i4> %ret
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}
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; CHECK-LABEL: test4
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; CHECK: movl
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; CHECK-NEXT: shrl
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; CHECK-NEXT: andl
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; CHECK-NEXT: movl
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; CHECK-NEXT: andl
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; CHECK-NEXT: vmovd
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movl
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; CHECK-NEXT: shrl
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movl
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; CHECK-NEXT: shrl
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movl
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; CHECK-NEXT: shrl
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movl
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; CHECK-NEXT: shrl
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movl
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; CHECK-NEXT: shrl
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movl
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; CHECK-NEXT: shrl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movq
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; CHECK-NEXT: shrq
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movq
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; CHECK-NEXT: shrq
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movq
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; CHECK-NEXT: shrq
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movq
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; CHECK-NEXT: shrq
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movq
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; CHECK-NEXT: shrq
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movq
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; CHECK-NEXT: shrq
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: movq
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; CHECK-NEXT: shrq
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; CHECK-NEXT: andl
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: shrq
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; CHECK-NEXT: vpinsrb
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; CHECK-NEXT: retq
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