Kalle Raiskila 8258135c90 Zap some redundant 'ori $?, $?, 0' from SPU. ...

Also remove some code that died in the process.
One now non-existant ori is checked for.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115306 91177308-0d34-0410-b5e6-96231b3b80d8

2010-10-01 09:20:01 +00:00

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useful-harnesses

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2009-01-01-BrCond.ll

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2010-04-07-DbgValueOtherTargets.ll

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and_ops.ll

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arg_ret.ll

Zap some redundant 'ori $?, $?, 0' from SPU.

2010-10-01 09:20:01 +00:00

bigstack.ll

Have SPU handle halfvec stores aligned by 8 bytes.

2010-08-09 16:33:00 +00:00

bss.ll

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call_indirect.ll

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call.ll

Fix SPU BE to use all the available return registers.

2010-08-24 11:50:48 +00:00

crash.ll

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ctpop.ll

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dg.exp

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dp_farith.ll

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eqv.ll

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extract_elt.ll

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fcmp32.ll

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fcmp64.ll

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fdiv.ll

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fneg-fabs.ll

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i8ops.ll

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i64ops.ll

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icmp8.ll

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icmp16.ll

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icmp32.ll

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icmp64.ll

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immed16.ll

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immed32.ll

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immed64.ll

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int2fp.ll

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intrinsics_branch.ll

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intrinsics_float.ll

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intrinsics_logical.ll

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jumptable.ll

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loads.ll

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mul_ops.ll

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mul-with-overflow.ll

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nand.ll

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or_ops.ll

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private.ll

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rotate_ops.ll

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select_bits.ll

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sext128.ll

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shift_ops.ll

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shuffles.ll

Fix CellSPU vector shuffles, again.

2010-09-08 11:53:38 +00:00

sp_farith.ll

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stores.ll

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storestruct.ll

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struct_1.ll

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sub_ops.ll

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trunc.ll

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v2f32.ll

Remove all traces of v2[i,f]32 on SPU.

2010-08-18 10:04:39 +00:00

v2i32.ll

Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.

2010-09-16 12:29:33 +00:00

vec_const.ll

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vecinsert.ll

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