llvm-6502/lib/CodeGen
2013-02-24 01:26:05 +00:00
..
AsmPrinter Use getSplitDebugFilename when constructing the skeleton cu and 2013-02-22 23:50:08 +00:00
SelectionDAG SelectionDAG compile time improvement. 2013-02-22 23:33:30 +00:00
AggressiveAntiDepBreaker.cpp Remove special-casing of return blocks for liveness. 2013-02-05 18:21:52 +00:00
AggressiveAntiDepBreaker.h
AllocationOrder.cpp Assert that the target provided hints are in the allocation order. 2013-02-19 18:41:01 +00:00
AllocationOrder.h Limit the search space in RAGreedy::tryEvict(). 2013-01-12 00:57:44 +00:00
Analysis.cpp Remove unused parameter. Also use the AttributeSet query methods instead of the Attribute query methods. 2013-01-18 21:50:24 +00:00
AntiDepBreaker.h
BasicTargetTransformInfo.cpp ARM cost model: Address computation in vector mem ops not free 2013-02-08 14:50:48 +00:00
BranchFolding.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
BranchFolding.h
CalcSpillWeights.cpp
CallingConvLower.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
CMakeLists.txt Split TargetLowering into a CodeGen and a SelectionDAG part. 2013-01-11 20:05:37 +00:00
CodeGen.cpp Switch TargetTransformInfo from an immutable analysis pass that requires 2013-01-07 01:37:14 +00:00
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp Remove special-casing of return blocks for liveness. 2013-02-05 18:21:52 +00:00
CriticalAntiDepBreaker.h This patch addresses bug 15031. 2013-01-28 18:36:58 +00:00
DeadMachineInstructionElim.cpp Remove special-casing of return blocks for liveness. 2013-02-05 18:21:52 +00:00
DFAPacketizer.cpp
DwarfEHPrepare.cpp Split TargetLowering into a CodeGen and a SelectionDAG part. 2013-01-11 20:05:37 +00:00
EarlyIfConversion.cpp Move MachineTraceMetrics.h into include/llvm/CodeGen. 2013-01-17 01:06:04 +00:00
EdgeBundles.cpp
ExecutionDepsFix.cpp
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp Re-apply r175688, with the changes suggested by Jakob in PR15320. 2013-02-21 22:16:43 +00:00
GCMetadata.cpp Fix GCMetadaPrinter::finishAssembly not executed, patch by Yiannis Tsiouris. 2013-02-19 16:51:44 +00:00
GCMetadataPrinter.cpp
GCStrategy.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
IfConversion.cpp Avoid creating duplicate CFG edges in the IfConversion pass. 2013-01-24 23:59:08 +00:00
InlineSpiller.cpp
InterferenceCache.cpp
InterferenceCache.h
IntrinsicLowering.cpp Revert "Add LLVMContext::emitWarning methods and use them. <rdar://problem/12867368>" 2013-02-08 21:48:29 +00:00
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp Correct indentation for dumping LexicalScope. 2013-02-02 00:02:03 +00:00
LiveDebugVariables.cpp Clean up LDV, no functionality change. 2013-02-13 20:23:48 +00:00
LiveDebugVariables.h Clean up LDV, no functionality change. 2013-02-13 20:23:48 +00:00
LiveInterval.cpp Don't allocate memory in LiveInterval::join(). 2013-02-20 23:51:10 +00:00
LiveIntervalAnalysis.cpp Make some fixes for LiveInterval repair with debug info. Debug value 2013-02-23 10:25:25 +00:00
LiveIntervalUnion.cpp
LiveRangeCalc.cpp Copy single reaching defs directly into the LiveInterval. 2013-02-20 23:08:26 +00:00
LiveRangeCalc.h Copy single reaching defs directly into the LiveInterval. 2013-02-20 23:08:26 +00:00
LiveRangeEdit.cpp
LiveRegMatrix.cpp
LiveStackAnalysis.cpp
LiveVariables.cpp Remove special-casing of return blocks for liveness. 2013-02-05 18:21:52 +00:00
LLVMBuild.txt Extracted ObjCARC.cpp into its own library libLLVMObjCARCOpts in preparation for refactoring the ARC Optimizer. 2013-01-28 01:35:51 +00:00
LLVMTargetMachine.cpp Fix GCMetadaPrinter::finishAssembly not executed, patch by Yiannis Tsiouris. 2013-02-19 16:51:44 +00:00
LocalStackSlotAllocation.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
MachineBasicBlock.cpp Remove use of reverse iterators in repairIntervalsInRange(). While they were 2013-02-17 11:09:00 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp Split TargetLowering into a CodeGen and a SelectionDAG part. 2013-01-11 20:05:37 +00:00
MachineBranchProbabilityInfo.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp
MachineCSE.cpp
MachineDominators.cpp
MachineFunction.cpp Revert 172027 and 174336. Remove diagnostics about over-aligned stack objects. 2013-02-08 20:35:15 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
MachineFunctionPrinterPass.cpp
MachineInstr.cpp Remove liveout lists from MachineRegisterInfo. 2013-02-05 18:21:56 +00:00
MachineInstrBundle.cpp Move an assertion so it doesn't dereference end(). 2013-01-04 22:17:31 +00:00
MachineLICM.cpp Split TargetLowering into a CodeGen and a SelectionDAG part. 2013-01-11 20:05:37 +00:00
MachineLoopInfo.cpp
MachineModuleInfo.cpp small fixes to enable the reuse of the pass manager across multiple modules 2013-01-04 18:04:42 +00:00
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachinePostDominators.cpp
MachineRegisterInfo.cpp Remove liveout lists from MachineRegisterInfo. 2013-02-05 18:21:56 +00:00
MachineScheduler.cpp Use const reference instead of vector object when passing an argument to 2013-02-16 15:47:26 +00:00
MachineSink.cpp
MachineSSAUpdater.cpp
MachineTraceMetrics.cpp Move MachineTraceMetrics.h into include/llvm/CodeGen. 2013-01-17 01:06:04 +00:00
MachineVerifier.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
Passes.cpp Fix a typo. 2013-02-10 06:42:34 +00:00
PeepholeOptimizer.cpp
PHIElimination.cpp Don't rely on the isDead() MachineOperand flag when updating LiveIntervals. 2013-02-21 08:51:58 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Remove special-casing of return blocks for liveness. 2013-02-05 18:21:52 +00:00
ProcessImplicitDefs.cpp
PrologEpilogInserter.cpp Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo 2013-02-21 20:05:00 +00:00
PrologEpilogInserter.h
PseudoSourceValue.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
README.txt
RegAllocBase.cpp
RegAllocBase.h
RegAllocBasic.cpp
RegAllocFast.cpp Make RAFast::UsedInInstr indexed by register units. 2013-02-21 19:35:21 +00:00
RegAllocGreedy.cpp Limit the search space in RAGreedy::tryEvict(). 2013-01-12 00:57:44 +00:00
RegAllocPBQP.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
RegisterClassInfo.cpp Precompute some information about register costs. 2013-01-12 00:54:59 +00:00
RegisterCoalescer.cpp RegisterCoalescer::reMaterializeTrivialDef() can constrain the destination 2013-02-14 03:25:24 +00:00
RegisterCoalescer.h
RegisterPressure.cpp Replace erase loop with std::remove_if. 2013-02-16 17:06:38 +00:00
RegisterScavenging.cpp [PEI] Pass the frame index operand number to the eliminateFrameIndex function. 2013-01-31 20:02:54 +00:00
ScheduleDAG.cpp Replace loop with std::find. 2013-02-16 17:06:32 +00:00
ScheduleDAGInstrs.cpp Equal treatment of labels and other terminators in MI DAG construction. 2013-02-12 16:36:03 +00:00
ScheduleDAGPrinter.cpp ScheduleDAG: colorize the DOT graph and improve formatting. 2013-01-25 07:45:25 +00:00
ScoreboardHazardRecognizer.cpp
ShadowStackGC.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
ShrinkWrapping.cpp
SjLjEHPrepare.cpp Split TargetLowering into a CodeGen and a SelectionDAG part. 2013-01-11 20:05:37 +00:00
SlotIndexes.cpp Make some fixes for LiveInterval repair with debug info. Debug value 2013-02-23 10:25:25 +00:00
Spiller.cpp
Spiller.h
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp
SplitKit.h
StackColoring.cpp More const correcting of stack coloring. 2013-02-19 06:02:40 +00:00
StackProtector.cpp Add the heuristic to differentiate SSPStrong from SSPRequired. 2013-01-23 06:43:53 +00:00
StackSlotColoring.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
StrongPHIElimination.cpp
TailDuplication.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
TargetFrameLoweringImpl.cpp
TargetInstrInfo.cpp Add static cast to unsigned char whenever a character classification function is called with a signed char argument, in order to avoid assertions in Windows Debug configuration. 2013-02-12 21:21:59 +00:00
TargetLoweringBase.cpp Update TargetLowering ivars for name policy. 2013-02-20 21:13:59 +00:00
TargetLoweringObjectFileImpl.cpp [MC/Mach-O] Implement integrated assembler support for linker options. 2013-01-18 19:37:00 +00:00
TargetOptionsImpl.cpp
TargetRegisterInfo.cpp Remove unneeded "TargetMachine.h" #includes. 2013-02-09 20:54:05 +00:00
TargetSchedule.cpp
TwoAddressInstructionPass.cpp Add a use of an otherwise unused variable to remove a warning in non-Asserts 2013-02-24 01:26:05 +00:00
UnreachableBlockElim.cpp Move all of the header files which are involved in modelling the LLVM IR 2013-01-02 11:36:10 +00:00
VirtRegMap.cpp

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.