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llvm-6502/lib/Target/R600
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Rafael Espindola a23cc6a1ea Add r224985 back with fixes. 
The fixes are to note that AArch64 has additional restrictions on when local
relocations can be used. In particular, ld64 requires that relocations to
cstring/cfstrings use linker visible symbols.

Original message:

In an assembly expression like

bar:
  .long L0 + 1

the intended semantics is that bar will contain a pointer one byte past L0.

In sections that are merged by content (strings, 4 byte constants, etc), a
single position in the section doesn't give the linker enough information.
For example, it would not be able to tell a relocation must point to the
end of a string, since that would look just like the start of the next.

The solution used in ELF to use relocation with symbols if there is a non-zero
addend.

In MachO before this patch we would just keep all symbols in some sections.

This would miss some cases (only cstrings on x86_64 were implemented) and was
inefficient since most relocations have an addend of 0 and can be represented
without the symbol.

This patch implements the non-zero addend logic for MachO too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226503 91177308-0d34-0410-b5e6-96231b3b80d8
2015-01-19 21:11:14 +00:00
..
AsmParser R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
InstPrinter [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
MCTargetDesc Add r224985 back with fixes. 2015-01-19 21:11:14 +00:00
TargetInfo R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPU.h R600/SI: Spill VGPRs to scratch space for compute shaders 2015-01-14 15:42:31 +00:00
AMDGPU.td R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
AMDGPUAlwaysInlinePass.cpp Reapply: R600: Make sure to inline all internal functions 2014-11-03 19:49:05 +00:00
AMDGPUAsmPrinter.cpp std::unique_ptrify the MCStreamer argument to createAsmPrinter 2015-01-18 20:29:04 +00:00
AMDGPUAsmPrinter.h std::unique_ptrify the MCStreamer argument to createAsmPrinter 2015-01-18 20:29:04 +00:00
AMDGPUCallingConv.td
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUInstrInfo.cpp R600/SI: Don't shrink instructions whose e32 encoding doesn't exist 2015-01-15 18:42:51 +00:00
AMDGPUInstrInfo.h R600/SI: Don't shrink instructions whose e32 encoding doesn't exist 2015-01-15 18:42:51 +00:00
AMDGPUInstrInfo.td R600/SI: Add class intrinsic 2015-01-06 23:00:37 +00:00
AMDGPUInstructions.td R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32 2015-01-15 23:58:35 +00:00
AMDGPUIntrinsicInfo.cpp
AMDGPUIntrinsicInfo.h
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp R600/SI: Use RegisterOperands to specify which operands can accept immediates 2015-01-12 19:33:18 +00:00
AMDGPUISelLowering.cpp Implement new way of expanding extloads. 2015-01-14 01:35:17 +00:00
AMDGPUISelLowering.h R600: Implement getRecipEstimate 2015-01-13 20:53:23 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h Reapply "R600: Add new intrinsic to read work dimensions" 2014-10-14 20:05:26 +00:00
AMDGPUMCInstLower.cpp R600/SI: Don't shrink instructions whose e32 encoding doesn't exist 2015-01-15 18:42:51 +00:00
AMDGPUMCInstLower.h R600/SI: Don't shrink instructions whose e32 encoding doesn't exist 2015-01-15 18:42:51 +00:00
AMDGPUPromoteAlloca.cpp R600: Don't promote allocas when one of the users is a ptrtoint instruction 2014-10-31 20:52:04 +00:00
AMDGPURegisterInfo.cpp R600/SI: Enable inline assembly 2014-12-03 04:08:00 +00:00
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
AMDGPUSubtarget.h [cleanup] Re-sort all the #include lines in LLVM using 2015-01-14 11:23:27 +00:00
AMDGPUTargetMachine.cpp R600/SI: Spill VGPRs to scratch space for compute shaders 2015-01-14 15:42:31 +00:00
AMDGPUTargetMachine.h R600/SI: Add a stub GCNTargetMachine 2015-01-06 18:00:21 +00:00
AMDGPUTargetTransformInfo.cpp Fix broken doxygen annotations, NFC 2014-11-12 18:25:06 +00:00
AMDILCFGStructurizer.cpp
AMDKernelCodeT.h R600/SI: Emit amd_kernel_code_t header for AMDGPU environment 2014-12-02 22:00:07 +00:00
CaymanInstructions.td
CIInstructions.td R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
CMakeLists.txt R600/SI: Spill VGPRs to scratch space for compute shaders 2015-01-14 15:42:31 +00:00
EvergreenInstructions.td R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGs 2014-11-02 23:46:54 +00:00
LLVMBuild.txt R600/SI: Start implementing an assembler 2014-11-14 14:08:00 +00:00
Makefile R600/SI: Start implementing an assembler 2014-11-14 14:08:00 +00:00
Processors.td R600/SI: Define a schedule model 2015-01-14 01:13:19 +00:00
R600ClauseMergePass.cpp
R600ControlFlowFinalizer.cpp Remove unnecessary copying or replace it with moves in a bunch of places. 2014-10-04 16:55:56 +00:00
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td R600/SI: Start implementing an assembler 2014-11-14 14:08:00 +00:00
R600InstrInfo.cpp Remove unused argument to CreateTargetScheduleState and change 2014-10-09 01:59:35 +00:00
R600InstrInfo.h Remove unused argument to CreateTargetScheduleState and change 2014-10-09 01:59:35 +00:00
R600Instructions.td R600/SI: Use unordered not equal instructions 2014-12-11 22:15:35 +00:00
R600Intrinsics.td
R600ISelLowering.cpp [SelectionDAG] Allow targets to specify legality of extloads' result 2015-01-08 00:51:32 +00:00
R600ISelLowering.h
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp Eliminate some deep std::vector copies. NFC. 2014-10-03 18:33:16 +00:00
R600Packetizer.cpp
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
R700Instructions.td
SIAnnotateControlFlow.cpp
SIDefines.h R600/SI: Use RegisterOperands to specify which operands can accept immediates 2015-01-12 19:33:18 +00:00
SIFixSGPRCopies.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIFixSGPRLiveRanges.cpp R600/SI: Fix the FixSGPRLiveRanges pass 2014-09-24 01:33:24 +00:00
SIFoldOperands.cpp R600/SI: Add pattern for bitcasting fp immediates to integers 2015-01-13 22:59:41 +00:00
SIInsertWaits.cpp R600/SI: Insert s_waitcnt before s_barrier instructions. 2015-01-06 19:52:07 +00:00
SIInstrFormats.td R600/SI: Add common class VOPAnyCommon 2015-01-15 18:42:44 +00:00
SIInstrInfo.cpp R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI 2015-01-15 18:43:01 +00:00
SIInstrInfo.h R600/SI: Don't shrink instructions whose e32 encoding doesn't exist 2015-01-15 18:42:51 +00:00
SIInstrInfo.td R600/SI: Fix trailing comma with modifiers 2015-01-15 23:17:03 +00:00
SIInstructions.td R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32 2015-01-15 23:58:35 +00:00
SIIntrinsics.td
SIISelLowering.cpp R600/SI: Fix bad code with unaligned byte vector loads 2015-01-14 01:35:22 +00:00
SIISelLowering.h R600/SI: Fix bad code with unaligned byte vector loads 2015-01-14 01:35:22 +00:00
SILoadStoreOptimizer.cpp R600/SI: Fix live range error hidden by SIFoldOperands 2014-12-03 05:22:29 +00:00
SILowerControlFlow.cpp R600/SI: Add pattern for bitcasting fp immediates to integers 2015-01-13 22:59:41 +00:00
SILowerI1Copies.cpp R600/SI: Remove VReg_32 register class 2015-01-07 20:59:25 +00:00
SIMachineFunctionInfo.cpp R600/SI: Spill VGPRs to scratch space for compute shaders 2015-01-14 15:42:31 +00:00
SIMachineFunctionInfo.h R600/SI: Spill VGPRs to scratch space for compute shaders 2015-01-14 15:42:31 +00:00
SIPrepareScratchRegs.cpp R600/SI: Spill VGPRs to scratch space for compute shaders 2015-01-14 15:42:31 +00:00
SIRegisterInfo.cpp R600/SI: Spill VGPRs to scratch space for compute shaders 2015-01-14 15:42:31 +00:00
SIRegisterInfo.h R600/SI: Spill VGPRs to scratch space for compute shaders 2015-01-14 15:42:31 +00:00
SIRegisterInfo.td R600/SI: Use RegisterOperands to specify which operands can accept immediates 2015-01-12 19:33:18 +00:00
SISchedule.td R600/SI: Define a schedule model 2015-01-14 01:13:19 +00:00
SIShrinkInstructions.cpp R600/SI: Don't shrink instructions whose e32 encoding doesn't exist 2015-01-15 18:42:51 +00:00
SITypeRewriter.cpp Revert "IR: MDNode => Value" 2014-11-11 21:30:22 +00:00
VIInstrFormats.td R600/SI: Add VI instructions 2014-12-07 12:18:57 +00:00
VIInstructions.td R600/SI: Unify VOP2 instructions which are VOP3-only on VI 2015-01-15 18:43:06 +00:00