Matt Arsenault 2220408e1a Support REG_SEQUENCE in tablegen. ... The problem is mostly that variadic output instruction aren't handled, so it is rejected for having an inconsistent number of operands, and then the right number of operands isn't emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@221117 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-02 23:46:51 +00:00
..
AsmMatcherEmitter.cpp
AsmWriterEmitter.cpp
AsmWriterInst.cpp
AsmWriterInst.h
CallingConvEmitter.cpp	[tablegen] Add CustomCallingConv and use it to tablegen-erate the outermost parts of the Mips O32 implementation	2014-11-01 17:38:22 +00:00
CMakeLists.txt
CodeEmitterGen.cpp
CodeGenDAGPatterns.cpp	Support REG_SEQUENCE in tablegen.	2014-11-02 23:46:51 +00:00
CodeGenDAGPatterns.h
CodeGenInstruction.cpp
CodeGenInstruction.h
CodeGenIntrinsics.h
CodeGenMapTable.cpp
CodeGenRegisters.cpp
CodeGenRegisters.h
CodeGenSchedule.cpp
CodeGenSchedule.h
CodeGenTarget.cpp
CodeGenTarget.h
CTagsEmitter.cpp
DAGISelEmitter.cpp
DAGISelMatcher.cpp
DAGISelMatcher.h	Fix missing C++ mode comment	2014-11-02 23:46:44 +00:00
DAGISelMatcherEmitter.cpp
DAGISelMatcherGen.cpp	Support REG_SEQUENCE in tablegen.	2014-11-02 23:46:51 +00:00
DAGISelMatcherOpt.cpp
DFAPacketizerEmitter.cpp
DisassemblerEmitter.cpp
FastISelEmitter.cpp
FixedLenDecoderEmitter.cpp
InstrInfoEmitter.cpp
IntrinsicEmitter.cpp
LLVMBuild.txt
Makefile
module.modulemap
OptParserEmitter.cpp
PseudoLoweringEmitter.cpp
RegisterInfoEmitter.cpp
SequenceToOffsetTable.h
SubtargetEmitter.cpp
TableGen.cpp
TableGenBackends.h
tdtags
X86DisassemblerShared.h
X86DisassemblerTables.cpp	[AVX512] Extended avx512_sqrt_packed (sqrt instructions) to VL subset.	2014-10-28 18:15:20 +00:00
X86DisassemblerTables.h
X86ModRMFilters.cpp
X86ModRMFilters.h
X86RecognizableInstr.cpp
X86RecognizableInstr.h