LLVM backend for 6502
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Renato Golin 6215f78195 Elide repeated register operand in Thumb1 instructions
This patch makes the ARM backend transform 3 operand instructions such as
'adds/subs' to the 2 operand version of the same instruction if the first
two register operands are the same.

Example: 'adds r0, r0, #1' will is transformed to 'adds r0, #1'.

Currently for some instructions such as 'adds' if you try to assemble
'adds r0, r0, #8' for thumb v6m the assembler would throw an error message
because the immediate cannot be encoded using 3 bits.

The backend should be smart enough to transform the instruction to
'adds r0, #8', which allows for larger immediate constants.

Patch by Ranjeet Singh.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@218521 91177308-0d34-0410-b5e6-96231b3b80d8
2014-09-26 16:14:29 +00:00
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cmake Add CMake check for libatomic. 2014-09-12 11:08:59 +00:00
docs fix a typo in doumentation index. 2014-09-26 06:59:15 +00:00
examples Add doInitialization/doFinalization to DataLayoutPass. 2014-09-10 21:27:43 +00:00
include Target: Fix build breakage. 2014-09-26 02:57:05 +00:00
lib Elide repeated register operand in Thumb1 instructions 2014-09-26 16:14:29 +00:00
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test Elide repeated register operand in Thumb1 instructions 2014-09-26 16:14:29 +00:00
tools llvm-vtabledump: Small cleanup 2014-09-26 08:01:23 +00:00
unittests [Support] Add type-safe alternative to llvm::format() 2014-09-25 20:30:58 +00:00
utils [mips] Add CCValAssign::[ASZ]ExtUpper and CCPromoteToUpperBitsInType and handle struct's correctly on big-endian N32/N64 return values. 2014-09-25 12:15:05 +00:00
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CODE_OWNERS.TXT Add Tom Stellard's role as 3.5 release manager. 2014-09-12 08:07:31 +00:00
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