Evan Cheng 6267422318 Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74228 91177308-0d34-0410-b5e6-96231b3b80d8		2009-06-25 23:34:10 +00:00
..
Alpha
ARM	Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.	2009-06-25 23:34:10 +00:00
CBackend	Fix an erroneous check for isFNeg; the FNeg case is handled	2009-06-04 23:43:29 +00:00
CellSPU	Add some generic expansion logic for SMULO and UMULO. Fixes UMULO	2009-06-16 06:58:29 +00:00
CPP
Generic	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
IA64
Mips	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
MSP430	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
PowerPC	Don't grep the -debug output. This isn't the way to test changes.	2009-06-25 21:59:32 +00:00
SPARC	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00
Thumb	We should run these tests as well.	2009-06-24 21:36:26 +00:00
Thumb2	Select ADC, SBC, and RSC instead of the ADCS, SBCS, and RSCS when the carry bit def is not used.	2009-06-25 23:34:10 +00:00
X86	down with unwind info :)	2009-06-25 21:48:17 +00:00
XCore	Split the Add, Sub, and Mul instruction opcodes into separate	2009-06-04 22:49:04 +00:00