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62b8786d12
llvm-6502/lib/Target/XCore/Disassembler
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Richard Osborne 62b8786d12 Add instruction encodings / disassembly support 3r instructions. 
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-20 17:18:47 +00:00
..
CMakeLists.txt
LLVMBuild.txt
Makefile
XCoreDisassembler.cpp Add instruction encodings / disassembly support 3r instructions. 2013-01-20 17:18:47 +00:00