Johnny Chen 3a96122c4a Thumb2 BFC was insufficiently encoded. ... rdar://problem/9292717 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8		2011-04-15 22:52:15 +00:00
..
arm-tests.txt
dg.exp
invalid-Bcc-thumb.txt
invalid-BFI-arm.txt
invalid-CPS2p-arm.txt
invalid-CPS3p-arm.txt
invalid-DMB-thumb.txt
invalid-DSB-arm.txt
invalid-LDC-form-arm.txt
invalid-LDR_POST-arm.txt
invalid-LDR_PRE-arm.txt
invalid-LDRB_POST-arm.txt
invalid-LDRD_PRE-thumb.txt	Add sanity check for Ld/St Dual forms of Thumb2 instructions.	2011-04-12 23:31:00 +00:00
invalid-LDRrs-arm.txt
invalid-LDRT-arm.txt
invalid-LSL-regform.txt
invalid-MCR-arm.txt
invalid-MOVr-arm.txt
invalid-MOVs-arm.txt
invalid-MOVs-LSL-arm.txt
invalid-MOVTi16-arm.txt
invalid-MSRi-arm.txt
invalid-RFEorLDMIA-arm.txt
invalid-RSC-arm.txt
invalid-SBFX-arm.txt
invalid-SMLAD-arm.txt
invalid-SRS-arm.txt
invalid-SSAT-arm.txt
invalid-STMIA_UPD-thumb.txt
invalid-STRBrs-arm.txt
invalid-SXTB-arm.txt
invalid-t2Bcc-thumb.txt	Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).	2011-04-13 21:35:49 +00:00
invalid-t2LDRBT-thumb.txt	The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.	2011-04-13 21:04:32 +00:00
invalid-t2LDREXD-thumb.txt	Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.	2011-04-14 19:13:28 +00:00
invalid-t2LDRSHi8-thumb.txt	Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.	2011-04-13 19:46:05 +00:00
invalid-t2LDRSHi12-thumb.txt	Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings as such.	2011-04-13 19:46:05 +00:00
invalid-t2STR_POST-thumb.txt
invalid-t2STRD_PRE-thumb.txt	Add sanity check for Ld/St Dual forms of Thumb2 instructions.	2011-04-12 23:31:00 +00:00
invalid-t2STREXB-thumb.txt	Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.	2011-04-14 19:13:28 +00:00
invalid-t2STREXD-thumb.txt	Add sanity checkings for Thumb2 Load/Store Register Exclusive family of operations.	2011-04-14 19:13:28 +00:00
invalid-UMAAL-arm.txt
invalid-UQADD8-arm.txt
invalid-VLD1DUPq8_UPD-arm.txt	The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions	2011-04-15 00:10:45 +00:00
invalid-VLD3DUPd32_UPD-thumb.txt	A8.6.315 VLD3 (single 3-element structure to all lanes)	2011-04-15 22:49:08 +00:00
invalid-VLDMSDB_UPD-arm.txt
invalid-VQADD-arm.txt
invalid-VST2b32_UPD-arm.txt
neon-tests.txt	The ARM disassembler did not handle the alignment correctly for VLD*DUP* instructions	2011-04-15 00:10:45 +00:00
thumb-printf.txt
thumb-tests.txt	Thumb2 BFC was insufficiently encoded.	2011-04-15 22:52:15 +00:00