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AsmParser
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R600/SI: Add a stub GCNTargetMachine
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2015-01-06 18:00:21 +00:00 |
InstPrinter
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[cleanup] Re-sort all the #include lines in LLVM using
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2015-01-14 11:23:27 +00:00 |
MCTargetDesc
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Revert "Add r224985 back with two fixes."
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2015-01-14 19:07:23 +00:00 |
TargetInfo
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R600/SI: Add a stub GCNTargetMachine
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2015-01-06 18:00:21 +00:00 |
AMDGPU.h
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
AMDGPU.td
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R600/SI: Add VI instructions
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2014-12-07 12:18:57 +00:00 |
AMDGPUAlwaysInlinePass.cpp
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Reapply: R600: Make sure to inline all internal functions
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2014-11-03 19:49:05 +00:00 |
AMDGPUAsmPrinter.cpp
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std::unique_ptrify the MCStreamer argument to createAsmPrinter
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2015-01-18 20:29:04 +00:00 |
AMDGPUAsmPrinter.h
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std::unique_ptrify the MCStreamer argument to createAsmPrinter
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2015-01-18 20:29:04 +00:00 |
AMDGPUCallingConv.td
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AMDGPUFrameLowering.cpp
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AMDGPUFrameLowering.h
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AMDGPUInstrInfo.cpp
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
AMDGPUInstrInfo.h
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
AMDGPUInstrInfo.td
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R600/SI: Add class intrinsic
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2015-01-06 23:00:37 +00:00 |
AMDGPUInstructions.td
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R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
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2015-01-15 23:58:35 +00:00 |
AMDGPUIntrinsicInfo.cpp
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AMDGPUIntrinsicInfo.h
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AMDGPUIntrinsics.td
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AMDGPUISelDAGToDAG.cpp
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R600/SI: Use RegisterOperands to specify which operands can accept immediates
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2015-01-12 19:33:18 +00:00 |
AMDGPUISelLowering.cpp
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Implement new way of expanding extloads.
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2015-01-14 01:35:17 +00:00 |
AMDGPUISelLowering.h
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R600: Implement getRecipEstimate
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2015-01-13 20:53:23 +00:00 |
AMDGPUMachineFunction.cpp
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R600/SI: Add preliminary support for flat address space
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2014-09-15 15:41:53 +00:00 |
AMDGPUMachineFunction.h
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Reapply "R600: Add new intrinsic to read work dimensions"
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2014-10-14 20:05:26 +00:00 |
AMDGPUMCInstLower.cpp
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
AMDGPUMCInstLower.h
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
AMDGPUPromoteAlloca.cpp
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R600: Don't promote allocas when one of the users is a ptrtoint instruction
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2014-10-31 20:52:04 +00:00 |
AMDGPURegisterInfo.cpp
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R600/SI: Enable inline assembly
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2014-12-03 04:08:00 +00:00 |
AMDGPURegisterInfo.h
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AMDGPURegisterInfo.td
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AMDGPUSubtarget.cpp
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[cleanup] Re-sort all the #include lines in LLVM using
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2015-01-14 11:23:27 +00:00 |
AMDGPUSubtarget.h
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[cleanup] Re-sort all the #include lines in LLVM using
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2015-01-14 11:23:27 +00:00 |
AMDGPUTargetMachine.cpp
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
AMDGPUTargetMachine.h
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R600/SI: Add a stub GCNTargetMachine
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2015-01-06 18:00:21 +00:00 |
AMDGPUTargetTransformInfo.cpp
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Fix broken doxygen annotations, NFC
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2014-11-12 18:25:06 +00:00 |
AMDILCFGStructurizer.cpp
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AMDKernelCodeT.h
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R600/SI: Emit amd_kernel_code_t header for AMDGPU environment
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2014-12-02 22:00:07 +00:00 |
CaymanInstructions.td
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CIInstructions.td
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R600/SI: Add VI instructions
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2014-12-07 12:18:57 +00:00 |
CMakeLists.txt
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
EvergreenInstructions.td
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R600/SI: Use REG_SEQUENCE instead of INSERT_SUBREGs
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2014-11-02 23:46:54 +00:00 |
LLVMBuild.txt
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R600/SI: Start implementing an assembler
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2014-11-14 14:08:00 +00:00 |
Makefile
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R600/SI: Start implementing an assembler
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2014-11-14 14:08:00 +00:00 |
Processors.td
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R600/SI: Define a schedule model
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2015-01-14 01:13:19 +00:00 |
R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp
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Remove unnecessary copying or replace it with moves in a bunch of places.
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2014-10-04 16:55:56 +00:00 |
R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp
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R600InstrFormats.td
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R600/SI: Start implementing an assembler
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2014-11-14 14:08:00 +00:00 |
R600InstrInfo.cpp
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Remove unused argument to CreateTargetScheduleState and change
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2014-10-09 01:59:35 +00:00 |
R600InstrInfo.h
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Remove unused argument to CreateTargetScheduleState and change
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2014-10-09 01:59:35 +00:00 |
R600Instructions.td
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R600/SI: Use unordered not equal instructions
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2014-12-11 22:15:35 +00:00 |
R600Intrinsics.td
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R600ISelLowering.cpp
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[SelectionDAG] Allow targets to specify legality of extloads' result
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2015-01-08 00:51:32 +00:00 |
R600ISelLowering.h
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R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp
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Fix float division-by-zero in R600 scheduler.
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2014-09-17 17:47:21 +00:00 |
R600MachineScheduler.h
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R600OptimizeVectorRegisters.cpp
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Eliminate some deep std::vector copies. NFC.
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2014-10-03 18:33:16 +00:00 |
R600Packetizer.cpp
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R600RegisterInfo.cpp
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R600RegisterInfo.h
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R600RegisterInfo.td
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R600Schedule.td
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R600TextureIntrinsicsReplacer.cpp
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R700Instructions.td
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SIAnnotateControlFlow.cpp
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SIDefines.h
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R600/SI: Use RegisterOperands to specify which operands can accept immediates
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2015-01-12 19:33:18 +00:00 |
SIFixSGPRCopies.cpp
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R600/SI: Remove VReg_32 register class
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2015-01-07 20:59:25 +00:00 |
SIFixSGPRLiveRanges.cpp
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R600/SI: Fix the FixSGPRLiveRanges pass
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2014-09-24 01:33:24 +00:00 |
SIFoldOperands.cpp
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R600/SI: Add pattern for bitcasting fp immediates to integers
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2015-01-13 22:59:41 +00:00 |
SIInsertWaits.cpp
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R600/SI: Insert s_waitcnt before s_barrier instructions.
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2015-01-06 19:52:07 +00:00 |
SIInstrFormats.td
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R600/SI: Add common class VOPAnyCommon
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2015-01-15 18:42:44 +00:00 |
SIInstrInfo.cpp
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R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI
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2015-01-15 18:43:01 +00:00 |
SIInstrInfo.h
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
SIInstrInfo.td
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R600/SI: Fix trailing comma with modifiers
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2015-01-15 23:17:03 +00:00 |
SIInstructions.td
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R600/SI: Add patterns for v_cvt_{flr|rpi}_i32_f32
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2015-01-15 23:58:35 +00:00 |
SIIntrinsics.td
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SIISelLowering.cpp
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R600/SI: Fix bad code with unaligned byte vector loads
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2015-01-14 01:35:22 +00:00 |
SIISelLowering.h
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R600/SI: Fix bad code with unaligned byte vector loads
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2015-01-14 01:35:22 +00:00 |
SILoadStoreOptimizer.cpp
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R600/SI: Fix live range error hidden by SIFoldOperands
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2014-12-03 05:22:29 +00:00 |
SILowerControlFlow.cpp
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R600/SI: Add pattern for bitcasting fp immediates to integers
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2015-01-13 22:59:41 +00:00 |
SILowerI1Copies.cpp
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R600/SI: Remove VReg_32 register class
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2015-01-07 20:59:25 +00:00 |
SIMachineFunctionInfo.cpp
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
SIMachineFunctionInfo.h
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
SIPrepareScratchRegs.cpp
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
SIRegisterInfo.cpp
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
SIRegisterInfo.h
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R600/SI: Spill VGPRs to scratch space for compute shaders
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2015-01-14 15:42:31 +00:00 |
SIRegisterInfo.td
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R600/SI: Use RegisterOperands to specify which operands can accept immediates
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2015-01-12 19:33:18 +00:00 |
SISchedule.td
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R600/SI: Define a schedule model
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2015-01-14 01:13:19 +00:00 |
SIShrinkInstructions.cpp
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R600/SI: Don't shrink instructions whose e32 encoding doesn't exist
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2015-01-15 18:42:51 +00:00 |
SITypeRewriter.cpp
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Revert "IR: MDNode => Value"
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2014-11-11 21:30:22 +00:00 |
VIInstrFormats.td
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R600/SI: Add VI instructions
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2014-12-07 12:18:57 +00:00 |
VIInstructions.td
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R600/SI: Unify VOP2 instructions which are VOP3-only on VI
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2015-01-15 18:43:06 +00:00 |