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d64ba3ee62
%reg1025 = <sext> %reg1024 ... %reg1026 = SUBREG_TO_REG 0, %reg1024, 4 into this: %reg1025 = <sext> %reg1024 ... %reg1027 = EXTRACT_SUBREG %reg1025, 4 %reg1026 = SUBREG_TO_REG 0, %reg1027, 4 The problem here is that SUBREG_TO_REG is there to assert that an implicit zext occurs. It doesn't insert a zext instruction. If we allow the EXTRACT_SUBREG here, it will give us the value after the <sext>, not the original value of %reg1024 before <sext>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105741 91177308-0d34-0410-b5e6-96231b3b80d8
221 lines
7.9 KiB
C++
221 lines
7.9 KiB
C++
//===-- OptimizeExts.cpp - Optimize sign / zero extension instrs -----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs optimization of sign / zero extension instructions. It
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// may be extended to handle other instructions of similar property.
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//
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// On some targets, some instructions, e.g. X86 sign / zero extension, may
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// leave the source value in the lower part of the result. This pass will
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// replace (some) uses of the pre-extension value with uses of the sub-register
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// of the results.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "ext-opt"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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using namespace llvm;
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static cl::opt<bool> Aggressive("aggressive-ext-opt", cl::Hidden,
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cl::desc("Aggressive extension optimization"));
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STATISTIC(NumReuse, "Number of extension results reused");
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namespace {
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class OptimizeExts : public MachineFunctionPass {
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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MachineDominatorTree *DT; // Machine dominator tree
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public:
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static char ID; // Pass identification
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OptimizeExts() : MachineFunctionPass(&ID) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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if (Aggressive) {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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}
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private:
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bool OptimizeInstr(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &LocalMIs);
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};
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}
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char OptimizeExts::ID = 0;
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static RegisterPass<OptimizeExts>
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X("opt-exts", "Optimize sign / zero extensions");
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FunctionPass *llvm::createOptimizeExtsPass() { return new OptimizeExts(); }
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/// OptimizeInstr - If instruction is a copy-like instruction, i.e. it reads
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/// a single register and writes a single register and it does not modify
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/// the source, and if the source value is preserved as a sub-register of
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/// the result, then replace all reachable uses of the source with the subreg
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/// of the result.
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/// Do not generate an EXTRACT that is used only in a debug use, as this
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/// changes the code. Since this code does not currently share EXTRACTs, just
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/// ignore all debug uses.
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bool OptimizeExts::OptimizeInstr(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &LocalMIs) {
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bool Changed = false;
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LocalMIs.insert(MI);
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unsigned SrcReg, DstReg, SubIdx;
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if (TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) {
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if (TargetRegisterInfo::isPhysicalRegister(DstReg) ||
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TargetRegisterInfo::isPhysicalRegister(SrcReg))
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return false;
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MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(SrcReg);
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if (++UI == MRI->use_nodbg_end())
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// No other uses.
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return false;
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// Ok, the source has other uses. See if we can replace the other uses
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// with use of the result of the extension.
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SmallPtrSet<MachineBasicBlock*, 4> ReachedBBs;
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UI = MRI->use_nodbg_begin(DstReg);
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for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
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UI != UE; ++UI)
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ReachedBBs.insert(UI->getParent());
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bool ExtendLife = true;
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// Uses that are in the same BB of uses of the result of the instruction.
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SmallVector<MachineOperand*, 8> Uses;
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// Uses that the result of the instruction can reach.
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SmallVector<MachineOperand*, 8> ExtendedUses;
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UI = MRI->use_nodbg_begin(SrcReg);
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for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
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UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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MachineInstr *UseMI = &*UI;
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if (UseMI == MI)
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continue;
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if (UseMI->isPHI()) {
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ExtendLife = false;
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continue;
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}
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// It's an error to translate this:
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//
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// %reg1025 = <sext> %reg1024
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// ...
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// %reg1026 = SUBREG_TO_REG 0, %reg1024, 4
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//
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// into this:
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//
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// %reg1025 = <sext> %reg1024
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// ...
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// %reg1027 = EXTRACT_SUBREG %reg1025, 4
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// %reg1026 = SUBREG_TO_REG 0, %reg1027, 4
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//
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// The problem here is that SUBREG_TO_REG is there to assert that an
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// implicit zext occurs. It doesn't insert a zext instruction. If we allow
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// the EXTRACT_SUBREG here, it will give us the value after the <sext>,
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// not the original value of %reg1024 before <sext>.
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if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
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continue;
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (UseMBB == MBB) {
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// Local uses that come after the extension.
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if (!LocalMIs.count(UseMI))
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Uses.push_back(&UseMO);
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} else if (ReachedBBs.count(UseMBB))
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// Non-local uses where the result of extension is used. Always
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// replace these unless it's a PHI.
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Uses.push_back(&UseMO);
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else if (Aggressive && DT->dominates(MBB, UseMBB))
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// We may want to extend live range of the extension result in order
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// to replace these uses.
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ExtendedUses.push_back(&UseMO);
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else {
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// Both will be live out of the def MBB anyway. Don't extend live
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// range of the extension result.
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ExtendLife = false;
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break;
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}
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}
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if (ExtendLife && !ExtendedUses.empty())
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// Ok, we'll extend the liveness of the extension result.
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std::copy(ExtendedUses.begin(), ExtendedUses.end(),
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std::back_inserter(Uses));
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// Now replace all uses.
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if (!Uses.empty()) {
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SmallPtrSet<MachineBasicBlock*, 4> PHIBBs;
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// Look for PHI uses of the extended result, we don't want to extend the
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// liveness of a PHI input. It breaks all kinds of assumptions down
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// stream. A PHI use is expected to be the kill of its source values.
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UI = MRI->use_nodbg_begin(DstReg);
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for (MachineRegisterInfo::use_nodbg_iterator UE = MRI->use_nodbg_end();
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UI != UE; ++UI)
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if (UI->isPHI())
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PHIBBs.insert(UI->getParent());
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const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
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for (unsigned i = 0, e = Uses.size(); i != e; ++i) {
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MachineOperand *UseMO = Uses[i];
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MachineInstr *UseMI = UseMO->getParent();
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (PHIBBs.count(UseMBB))
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continue;
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unsigned NewVR = MRI->createVirtualRegister(RC);
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BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
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TII->get(TargetOpcode::EXTRACT_SUBREG), NewVR)
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.addReg(DstReg).addImm(SubIdx);
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UseMO->setReg(NewVR);
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++NumReuse;
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Changed = true;
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}
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}
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}
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return Changed;
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}
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bool OptimizeExts::runOnMachineFunction(MachineFunction &MF) {
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TM = &MF.getTarget();
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TII = TM->getInstrInfo();
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MRI = &MF.getRegInfo();
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DT = Aggressive ? &getAnalysis<MachineDominatorTree>() : 0;
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bool Changed = false;
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SmallPtrSet<MachineInstr*, 8> LocalMIs;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
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MachineBasicBlock *MBB = &*I;
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LocalMIs.clear();
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for (MachineBasicBlock::iterator MII = I->begin(), ME = I->end(); MII != ME;
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++MII) {
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MachineInstr *MI = &*MII;
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Changed |= OptimizeInstr(MI, MBB, LocalMIs);
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}
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}
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return Changed;
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}
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