Reid Kleckner 2ab3b563da X86 MC: Handle instructions like fxsave that match multiple operand sizes ... Instructions like 'fxsave' and control flow instructions like 'jne' match any operand size. The loop I added to the Intel syntax matcher assumed that using a different size would give a different instruction. Now it handles the case where we get the same instruction for different memory operand sizes. This also allows us to remove the hack we had for unsized absolute memory operands, because we can successfully match things like 'jnz' without reporting ambiguity. Removing this hack uncovered test case involving 'fadd' that was ambiguous. The memory operand could have been single or double precision. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216604 91177308-0d34-0410-b5e6-96231b3b80d8		2014-08-27 20:10:38 +00:00
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AArch64	MC: AsmLexer: handle multi-character CommentStrings correctly	2014-08-14 02:51:43 +00:00
ARM	ARM: correct toggling behaviour	2014-08-17 19:20:38 +00:00
AsmParser	MC: AsmLexer: handle multi-character CommentStrings correctly	2014-08-14 02:51:43 +00:00
COFF
Disassembler	[PowerPC] Add support for dcbtst and icbt (prefetch)	2014-08-23 23:21:04 +00:00
ELF
MachO
Markup
Mips	[mips] Add assembler support for .set arch=x directive.	2014-08-19 14:22:52 +00:00
PowerPC	[PowerPC] Add support for dcbtst and icbt (prefetch)	2014-08-23 23:21:04 +00:00
Sparc
SystemZ
X86	X86 MC: Handle instructions like fxsave that match multiple operand sizes	2014-08-27 20:10:38 +00:00