Arnold Schwaighofer d42730dc71 IfConverter: Use TargetSchedule for instruction latencies ... For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191671 91177308-0d34-0410-b5e6-96231b3b80d8		2013-09-30 15:28:56 +00:00
..
InstPrinter
MCTargetDesc	MC: Remove vestigial PCSymbol field from AsmInfo	2013-09-25 09:36:11 +00:00
TargetInfo
AMDGPU.h
AMDGPU.td
AMDGPUAsmPrinter.cpp
AMDGPUAsmPrinter.h
AMDGPUCallingConv.td	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
AMDGPUConvertToISA.cpp
AMDGPUFrameLowering.cpp
AMDGPUFrameLowering.h
AMDGPUIndirectAddressing.cpp	Even more spelling fixes for "instruction".	2013-09-28 13:42:22 +00:00
AMDGPUInstrInfo.cpp
AMDGPUInstrInfo.h
AMDGPUInstrInfo.td
AMDGPUInstructions.td	R600: Fix handling of NAN in comparison instructions	2013-09-28 02:50:50 +00:00
AMDGPUIntrinsics.td
AMDGPUISelDAGToDAG.cpp	ISelDAG: spot chain cycles involving MachineNodes	2013-09-22 08:21:56 +00:00
AMDGPUISelLowering.cpp	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
AMDGPUISelLowering.h	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
AMDGPUMachineFunction.cpp
AMDGPUMachineFunction.h
AMDGPUMCInstLower.cpp
AMDGPUMCInstLower.h
AMDGPURegisterInfo.cpp
AMDGPURegisterInfo.h
AMDGPURegisterInfo.td
AMDGPUSubtarget.cpp
AMDGPUSubtarget.h	Allow subtarget selection of the default MachineScheduler and document the interface.	2013-09-20 05:14:41 +00:00
AMDGPUTargetMachine.cpp	Allow subtarget selection of the default MachineScheduler and document the interface.	2013-09-20 05:14:41 +00:00
AMDGPUTargetMachine.h
AMDGPUTargetTransformInfo.cpp
AMDILBase.td
AMDILCFGStructurizer.cpp
AMDILInstrInfo.td
AMDILIntrinsicInfo.cpp
AMDILIntrinsicInfo.h
AMDILIntrinsics.td
AMDILISelLowering.cpp
AMDILRegisterInfo.td
CMakeLists.txt
LLVMBuild.txt
Makefile
Processors.td
R600ControlFlowFinalizer.cpp
R600Defines.h
R600EmitClauseMarkers.cpp
R600ExpandSpecialInstrs.cpp
R600InstrFormats.td
R600InstrInfo.cpp	IfConverter: Use TargetSchedule for instruction latencies	2013-09-30 15:28:56 +00:00
R600InstrInfo.h	IfConverter: Use TargetSchedule for instruction latencies	2013-09-30 15:28:56 +00:00
R600Instructions.td	R600: Fix handling of NAN in comparison instructions	2013-09-28 02:50:50 +00:00
R600Intrinsics.td
R600ISelLowering.cpp	R600: Fix handling of NAN in comparison instructions	2013-09-28 02:50:50 +00:00
R600ISelLowering.h	R600: Move fabs/fneg/sel folding logic into PostProcessIsel	2013-09-12 23:44:44 +00:00
R600MachineFunctionInfo.cpp
R600MachineFunctionInfo.h
R600MachineScheduler.cpp	R600: Don't use trans slot for instructions that read LDS source registers	2013-09-12 02:55:06 +00:00
R600MachineScheduler.h
R600OptimizeVectorRegisters.cpp
R600Packetizer.cpp	R600: Don't use trans slot for instructions that read LDS source registers	2013-09-12 02:55:06 +00:00
R600RegisterInfo.cpp
R600RegisterInfo.h
R600RegisterInfo.td	R600: Don't use trans slot for instructions that read LDS source registers	2013-09-12 02:55:06 +00:00
R600Schedule.td
R600TextureIntrinsicsReplacer.cpp
SIAnnotateControlFlow.cpp
SIDefines.h
SIFixSGPRCopies.cpp
SIInsertWaits.cpp
SIInstrFormats.td
SIInstrInfo.cpp
SIInstrInfo.h
SIInstrInfo.td	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
SIInstructions.td	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
SIIntrinsics.td	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
SIISelLowering.cpp	R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback	2013-09-12 02:55:14 +00:00
SIISelLowering.h
SILowerControlFlow.cpp
SIMachineFunctionInfo.cpp
SIMachineFunctionInfo.h
SIRegisterInfo.cpp
SIRegisterInfo.h
SIRegisterInfo.td
SISchedule.td
SITypeRewriter.cpp