Evan Cheng c36b7069b4 Do not model all INLINEASM instructions as having unmodelled side effects. ... Instead encode llvm IR level property "HasSideEffects" in an operand (shared with IsAlignStack). Added MachineInstrs::hasUnmodeledSideEffects() to check the operand when the instruction is an INLINEASM. This allows memory instructions to be moved around INLINEASM instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123044 91177308-0d34-0410-b5e6-96231b3b80d8		2011-01-07 23:50:32 +00:00
..
CMakeLists.txt
DAGCombiner.cpp	DAGCombine add (sext i1), X into sub X, (zext i1) if sext from i1 is illegal. The latter usually compiles into smaller code.	2010-12-22 23:17:45 +00:00
FastISel.cpp	If dbg_declare() or dbg_value() is not lowered by isel then emit DEBUG message instead of creating DBG_VALUE for undefined value in reg0.	2010-12-06 22:39:26 +00:00
FunctionLoweringInfo.cpp
InstrEmitter.cpp	Do not model all INLINEASM instructions as having unmodelled side effects.	2011-01-07 23:50:32 +00:00
InstrEmitter.h
LegalizeDAG.cpp	Remove TODO, these appear to be implemented.	2011-01-04 22:31:50 +00:00
LegalizeFloatTypes.cpp	PR5207: Rename overloaded APInt methods set(), clear(), flip() to	2010-12-01 08:53:58 +00:00
LegalizeIntegerTypes.cpp	Add some fairly duplicated code to let type legalization split illegal	2011-01-06 22:28:56 +00:00
LegalizeTypes.cpp	Fix the other problem reported in PR8582. Testcase and patch by	2011-01-06 23:45:22 +00:00
LegalizeTypes.h	Add some fairly duplicated code to let type legalization split illegal	2011-01-06 22:28:56 +00:00
LegalizeTypesGeneric.cpp	Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.	2010-11-23 03:31:01 +00:00
LegalizeVectorOps.cpp	Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.	2010-11-23 03:31:01 +00:00
LegalizeVectorTypes.cpp	Change EXTRACT_SUBVECTOR to require a constant index.	2011-01-07 04:58:56 +00:00
Makefile
ScheduleDAGFast.cpp	flags -> glue for selectiondag	2010-12-23 17:24:32 +00:00
ScheduleDAGList.cpp	Various bits of framework needed for precise machine-level selection	2010-12-24 05:03:26 +00:00
ScheduleDAGRRList.cpp	Minor cleanup related to my latest scheduler changes.	2010-12-24 07:10:19 +00:00
ScheduleDAGSDNodes.cpp	flags -> glue for selectiondag	2010-12-23 17:24:32 +00:00
ScheduleDAGSDNodes.h	rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for	2010-12-21 02:38:05 +00:00
SDNodeDbgValue.h	Merge System into Support.	2010-11-29 18:16:10 +00:00
SDNodeOrdering.h
SelectionDAG.cpp	Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy	2011-01-06 06:52:41 +00:00
SelectionDAGBuilder.cpp	Do not model all INLINEASM instructions as having unmodelled side effects.	2011-01-07 23:50:32 +00:00
SelectionDAGBuilder.h	Avoid zero extend bit test operands to pointer type if all the masks fit in	2011-01-06 01:02:44 +00:00
SelectionDAGISel.cpp	Do not model all INLINEASM instructions as having unmodelled side effects.	2011-01-07 23:50:32 +00:00
SelectionDAGPrinter.cpp	flags -> glue for selectiondag	2010-12-23 17:24:32 +00:00
TargetLowering.cpp	Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy	2011-01-06 06:52:41 +00:00
TargetSelectionDAGInfo.cpp