llvm-6502/lib/Target/SparcV9/SparcV9_F2.td
Misha Brukman dafa504341 * Broke up SparcV9.td into separate files as it was getting unmanageable
* Added some Format 4 classes, but not instructions
* Added notes on missing sections with FIXMEs
* Added RDCCR instr


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6388 91177308-0d34-0410-b5e6-96231b3b80d8
2003-05-29 03:31:43 +00:00

65 lines
1.6 KiB
C++

//===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
// vim:ft=cpp
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Format #2 classes
//
class F2 : InstV9 { // Format 2 instructions
bits<3> op2;
set op = 0; // Op = 0
set Inst{24-22} = op2;
}
// Format 2.1 instructions
class F2_1<string name> : F2 {
bits<5> rd;
bits<22> imm;
set Name = name;
set Inst{29-25} = rd;
set Inst{21-0} = imm;
}
class F2_br : F2 { // Format 2 Branch instruction
bit annul; // All branches have an annul bit
set Inst{29} = annul;
set isBranch = 1; // All instances are branch instructions
}
class F2_2<bits<4> cond, string name> : F2_br { // Format 2.2 instructions
bits<22> disp;
set Name = name;
set Inst{28-25} = cond;
set Inst{21-0} = disp;
}
class F2_3<bits<4> cond, string name> : F2_br { // Format 2.3 instructions
bits<2> cc;
bits<19> disp;
bit predict;
set Name = name;
set Inst{28-25} = cond;
set Inst{21-20} = cc;
set Inst{19} = predict;
set Inst{18-0} = disp;
}
class F2_4<bits<3> rcond, string name> : F2_br { // Format 2.4 instructions
// Variables exposed by the instruction...
bit predict;
bits<5> rs1;
bits<16> disp;
set Name = name;
set Inst{28} = 0;
set Inst{27-25} = rcond;
// Inst{24-22} = op2 field
set Inst{21-20} = disp{15-14};
set Inst{19} = predict;
set Inst{18-14} = rs1;
set Inst{13-0 } = disp{13-0};
}