Matt Arsenault add2e2ec8f R600/SI: Fix extra mov from legalizing 64-bit SALU ops. ...

Check the register class of each operand individually
to avoid an extra copy to a vgpr.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204662 91177308-0d34-0410-b5e6-96231b3b80d8

2014-03-24 20:08:13 +00:00

..

AArch64

[AArch64] Add SchedRW lists to NEON instructions.

2014-03-21 19:34:41 +00:00

ARM

Fix test command line to avoid generating output file.

2014-03-21 07:20:29 +00:00

CPP

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Generic

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Hexagon

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Inputs

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Mips

[mips] Correct lowering of VECTOR_SHUFFLE to VSHF.

2014-03-21 16:56:51 +00:00

MSP430

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NVPTX

Add test to test/CodeGen/NVPTX for "alloca buffer" arguments.

2014-03-24 16:52:30 +00:00

PowerPC

[PowerPC] Make use of VSX f64 <-> i64 conversion instructions

2014-03-23 05:35:00 +00:00

R600

R600/SI: Fix extra mov from legalizing 64-bit SALU ops.

2014-03-24 20:08:13 +00:00

SPARC

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SystemZ

[SystemZ] Add support for z196 float<->unsigned conversions

2014-03-21 10:56:30 +00:00

Thumb

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Thumb2

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X86

[X86][ISelDAG] Add missing fallback patterns for avx2 broadcast instructions.

2014-03-24 17:54:19 +00:00

XCore

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