mirror of
https://github.com/c64scene-ar/llvm-6502.git
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17470bee5f
floating point add/sub of appropriate shuffle vectors. Does not synthesize the 256 bit AVX versions because they work differently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140332 91177308-0d34-0410-b5e6-96231b3b80d8
195 lines
6.1 KiB
LLVM
195 lines
6.1 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mattr=+sse3,-avx | FileCheck %s -check-prefix=SSE3
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; RUN: llc < %s -march=x86-64 -mattr=-sse3,+avx | FileCheck %s -check-prefix=AVX
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; SSE3: haddpd1:
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; SSE3-NOT: vhaddpd
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; SSE3: haddpd
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; AVX: haddpd1:
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; AVX: vhaddpd
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define <2 x double> @haddpd1(<2 x double> %x, <2 x double> %y) {
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%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
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%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
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%r = fadd <2 x double> %a, %b
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ret <2 x double> %r
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}
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; SSE3: haddpd2:
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; SSE3-NOT: vhaddpd
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; SSE3: haddpd
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; AVX: haddpd2:
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; AVX: vhaddpd
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define <2 x double> @haddpd2(<2 x double> %x, <2 x double> %y) {
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%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 2>
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%b = shufflevector <2 x double> %y, <2 x double> %x, <2 x i32> <i32 2, i32 1>
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%r = fadd <2 x double> %a, %b
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ret <2 x double> %r
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}
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; SSE3: haddpd3:
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; SSE3-NOT: vhaddpd
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; SSE3: haddpd
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; AVX: haddpd3:
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; AVX: vhaddpd
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define <2 x double> @haddpd3(<2 x double> %x) {
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%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
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%b = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
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%r = fadd <2 x double> %a, %b
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ret <2 x double> %r
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}
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; SSE3: haddps1:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX: haddps1:
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; AVX: vhaddps
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define <4 x float> @haddps1(<4 x float> %x, <4 x float> %y) {
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%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: haddps2:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX: haddps2:
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; AVX: vhaddps
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define <4 x float> @haddps2(<4 x float> %x, <4 x float> %y) {
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%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
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%b = shufflevector <4 x float> %y, <4 x float> %x, <4 x i32> <i32 4, i32 7, i32 0, i32 3>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: haddps3:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX: haddps3:
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; AVX: vhaddps
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define <4 x float> @haddps3(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: haddps4:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX: haddps4:
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; AVX: vhaddps
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define <4 x float> @haddps4(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: haddps5:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX: haddps5:
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; AVX: vhaddps
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define <4 x float> @haddps5(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 2, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: haddps6:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX: haddps6:
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; AVX: vhaddps
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define <4 x float> @haddps6(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: haddps7:
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; SSE3-NOT: vhaddps
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; SSE3: haddps
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; AVX: haddps7:
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; AVX: vhaddps
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define <4 x float> @haddps7(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 undef, i32 undef>
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%r = fadd <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: hsubpd1:
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; SSE3-NOT: vhsubpd
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; SSE3: hsubpd
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; AVX: hsubpd1:
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; AVX: vhsubpd
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define <2 x double> @hsubpd1(<2 x double> %x, <2 x double> %y) {
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%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
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%b = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 3>
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%r = fsub <2 x double> %a, %b
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ret <2 x double> %r
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}
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; SSE3: hsubpd2:
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; SSE3-NOT: vhsubpd
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; SSE3: hsubpd
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; AVX: hsubpd2:
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; AVX: vhsubpd
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define <2 x double> @hsubpd2(<2 x double> %x) {
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%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
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%b = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 1, i32 undef>
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%r = fsub <2 x double> %a, %b
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ret <2 x double> %r
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}
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; SSE3: hsubps1:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; AVX: hsubps1:
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; AVX: vhsubps
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define <4 x float> @hsubps1(<4 x float> %x, <4 x float> %y) {
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%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: hsubps2:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; AVX: hsubps2:
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; AVX: vhsubps
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define <4 x float> @hsubps2(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 5, i32 7>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: hsubps3:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; AVX: hsubps3:
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; AVX: vhsubps
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define <4 x float> @hsubps3(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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; SSE3: hsubps4:
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; SSE3-NOT: vhsubps
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; SSE3: hsubps
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; AVX: hsubps4:
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; AVX: vhsubps
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define <4 x float> @hsubps4(<4 x float> %x) {
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%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
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%b = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
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%r = fsub <4 x float> %a, %b
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ret <4 x float> %r
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}
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